256Mb: x4, x8, x16 SDRAM
Electrical Specifications – IDD Parameters
command wake-ups should be repeated any time the tREF refresh requirement is excee-
ded.
4. AC operating and IDD test conditions have VIL = 0V and VIH = 3.0V using a measurement
reference level of 1.5V. If the input transition time is longer than 1ns, then the timing is
measured from VIL, max and VIH,min and no longer from the 1.5V midpoint. CLK should
always be 1.5V referenced to crossover. Refer to Micron technical note TN-48-09.
5. IDD specifications are tested after the device is properly initialized.
6. IDD is dependent on output loading and cycle rates. Specified values are obtained with
minimum cycle time and the outputs open.
7. The IDD current will increase or decrease proportionally according to the amount of fre-
quency alteration for the test condition.
8. Address transitions average one transition every two clocks.
9. For -75, CL = 3 and tCK = 7.5ns; for -7E, CL = 2 and tCK = 7.5ns.
10. Other input signals are allowed to transition no more than once every two clocks and
are otherwise at valid VIH or VIL levels.
11. CKE is HIGH during REFRESH command period tRFC (MIN) else CKE is LOW. The IDD6 limit
is actually a nominal value and does not result in a fail value.
12. Enables on-chip refresh and address counters.
13. PC100 specifies a maximum of 4pF.
14. PC100 specifies a maximum of 5pF.
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. R 10/12 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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