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MT48LC64M4A2FB1 参数 Datasheet PDF下载

MT48LC64M4A2FB1图片预览
型号: MT48LC64M4A2FB1
PDF下载: 下载PDF文件 查看货源
内容描述: SDR SDRAM [SDR SDRAM]
分类和应用: 动态存储器
文件页数/大小: 86 页 / 3693 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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256Mb: x4, x8, x16 SDRAM  
Electrical Specifications – AC Operating Conditions  
Table 12: Electrical Characteristics and Recommended AC Operating Conditions (Continued)  
Notes 1–5 apply to all parameters and conditions  
-6A  
-7E  
-75  
Parameter  
Symbol Min  
tXSR  
67  
Max  
Min  
Max  
Min  
Max  
Unit Notes  
Exit SELF REFRESH-to-ACTIVE command  
67  
75  
ns  
15  
Table 13: AC Functional Characteristics  
Notes 2–5 apply to all parameters and conditions  
Parameter  
Symbol  
tBDL  
tCCD  
tCDL  
tCKED  
tDAL  
-6A  
1
-7E  
1
1
1
1
4
2
0
0
2
0
2
1
2
3
2
-75  
Unit  
Notes  
16  
Last data-in to burst STOP command  
READ/WRITE command to READ/WRITE command  
Last data-in to new READ/WRITE command  
CKE to clock disable or power-down entry mode  
Data-in to ACTIVE command  
1
1
1
1
5
2
0
0
2
0
2
1
2
3
2
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
1
16  
1
16  
17  
5
2
0
0
2
0
2
1
2
3
2
1
18, 19  
19, 20  
16  
Data-in to PRECHARGE command  
tDPL  
DQM to input data delay  
tDQD  
tDQM  
tDQZ  
tDWD  
tMRD  
tPED  
DQM to data mask during WRITEs  
DQM to data High-Z during READs  
WRITE command to input data delay  
16  
16  
16  
LOAD MODE REGISTER command to ACTIVE or REFRESH command  
CKE to clock enable or power-down exit setup mode  
Last data-in to PRECHARGE command  
21  
17  
tRDL  
19, 20  
16  
Data-out High-Z from PRECHARGE command  
CL = 3  
CL = 2  
CL = 1  
tROH(3)  
tROH(2)  
tROH(1)  
16  
16  
1. Minimum specifications are used only to indicate the cycle time at which proper opera-  
tion over the full temperature range is ensured:  
0˚C TA +70˚C (commercial)  
Notes:  
-40˚C TA +85˚C (industrial)  
-40˚C TA +105˚C (automotive)  
2. An initial pause of 100μs is required after power-up, followed by two AUTO REFRESH  
commands, before proper device operation is ensured. (VDD and VDDQ must be powered  
up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH  
command wake-ups should be repeated any time the tREF refresh requirement is excee-  
ded.  
3. In addition to meeting the transition rate specification, the clock and CKE must transit  
between VIH and VIL (or between VIL and VIH) in a monotonic manner.  
4. Outputs measured at 1.5V with equivalent load:  
Q
50pF  
5. AC operating and IDD test conditions have VIL = 0V and VIH = 3.0V using a measurement  
reference level of 1.5V. If the input transition time is longer than 1ns, then the timing is  
PDF: 09005aef8091e6d1  
256Mb_sdr.pdf - Rev. R 10/12 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
28  
© 1999 Micron Technology, Inc. All rights reserved.  
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