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MT48LC4M32LFFC 参数 Datasheet PDF下载

MT48LC4M32LFFC图片预览
型号: MT48LC4M32LFFC
PDF下载: 下载PDF文件 查看货源
内容描述: 同步DRAM [SYNCHRONOUS DRAM]
分类和应用: 动态存储器
文件页数/大小: 61 页 / 1390 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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ADVANCE  
128Mb: x16, x32  
MOBILE SDRAM  
Operation  
Figure 3  
Activating a Specific Row in a  
Specific Bank  
BANK/ROW ACTIVATION  
Before any READ or WRITE commands can be issued  
to a bank within the SDRAM, a row in that bank must be  
“opened.” This is accomplished via the ACTIVE com-  
mand, which selects both the bank and the row to be  
activated (see Figure 3).  
CLK  
CKE  
CS#  
HIGH  
After opening a row (issuing an ACTIVE command), a  
READ or WRITE command may be issued to that row,  
t
t
subject to the RCD specification. RCD (MIN) should be  
divided by the clock period and rounded up to the next  
whole number to determine the earliest clock edge after  
the ACTIVE command on which a READ or WRITE com-  
RAS#  
t
mand can be entered. For example, a RCD specification  
of 20ns with a 125 MHz clock (8ns period) results in 2.5  
clocks, rounded to 3. This is reflected in Figure 4, which  
covers any case where 2 < RCD (MIN)/ CK 3. (The same  
procedure is used to convert other specification limits  
from time units to clock cycles.)  
CAS#  
WE#  
t
t
A subsequent ACTIVE command to a different row in  
the same bank can only be issued after the previous  
active row has been “closed” (precharged). The mini-  
mum time interval between successive ACTIVE com-  
ROW  
A0–A10, A11  
BA0, BA1  
ADDRESS  
t
mands to the same bank is defined by RC.  
BANK  
ADDRESS  
A subsequent ACTIVE command to another bank can  
be issued while the first bank is being accessed, which  
results in a reduction of total row-access overhead. The  
minimumtimeintervalbetweensuccessiveACTIVEcom-  
t
mands to different banks is defined by RRD.  
Figure 4  
t
t
t
Example: Meeting RCD (MIN) When 2 < RCD (MIN)/ CK  
3
T0  
T1  
T2  
T3  
T4  
CLK  
READ or  
WRITE  
COMMAND  
ACTIVE  
NOP  
NOP  
t
RCD  
DON’T CARE  
128Mb: x16, x32 Mobile SDRAM  
MobileY95W_3V_F.p65 – Rev. F; Pub. 9/02  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2002, Micron Technology, Inc.  
17  
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