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MT48LC4M16A2P-75G 参数 Datasheet PDF下载

MT48LC4M16A2P-75G图片预览
型号: MT48LC4M16A2P-75G
PDF下载: 下载PDF文件 查看货源
内容描述: SDR SDRAM MT48LC16M4A2 â ????梅格4 ×4× 4银行MT48LC8M8A2 â ???? 2梅格×8× 4银行MT48LC4M16A2 â ???? 1梅格×16× 4银行 [SDR SDRAM MT48LC16M4A2 – 4 Meg x 4 x 4 Banks MT48LC8M8A2 – 2 Meg x 8 x 4 Banks MT48LC4M16A2 – 1 Meg x 16 x 4 Banks]
分类和应用: 动态存储器
文件页数/大小: 83 页 / 3595 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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64Mb: x4, x8, x16 SDRAM  
Commands  
REFRESH  
AUTO REFRESH  
AUTO REFRESH is used during normal operation of the SDRAM and is analogous to  
CAS#-BEFORE-RAS# (CBR) refresh in conventional DRAMs. This command is nonper-  
sistent, so it must be issued each time a refresh is required. All active banks must be pre-  
charged prior to issuing an AUTO REFRESH command. The AUTO REFRESH command  
should not be issued until the minimum tRP has been met after the PRECHARGE com-  
mand, as shown in Bank/Row Activation (page 46).  
The addressing is generated by the internal refresh controller. This makes the address  
bits a “Don’t Care” during an AUTO REFRESH command. Regardless of device width,  
the 64Mb SDRAM requires 4096 AUTO REFRESH cycles every 64ms (commercial and  
industrial) or 16ms (automotive). Providing a distributed AUTO REFRESH command  
every 15.625μs (commercial and industrial) or 3.906μs (automotive) will meet the re-  
fresh requirement and ensure that each row is refreshed. Alternatively, 4096 AUTO RE-  
FRESH commands can be issued in a burst at the minimum cycle rate (tRFC), once ev-  
ery 64ms (commercial and industrial) or 16ms (automotive).  
SELF REFRESH  
The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest  
of the system is powered-down. When in the self refresh mode, the SDRAM retains data  
without external clocking.  
The SELF REFRESH command is initiated like an AUTO REFRESH command except  
CKE is disabled (LOW). After the SELF REFRESH command is registered, all the inputs  
to the SDRAM become a “Don’t Care” with the exception of CKE, which must remain  
LOW.  
After self refresh mode is engaged, the SDRAM provides its own internal clocking, caus-  
ing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self re-  
fresh mode for a minimum period equal to tRAS and may remain in self refresh mode  
for an indefinite period beyond that.  
The procedure for exiting self refresh requires a sequence of commands. First, CLK  
must be stable (stable clock is defined as a signal cycling within timing constraints  
specified for the clock pin) prior to CKE going back HIGH. After CKE is HIGH, the  
SDRAM must have NOP commands issued (a minimum of two clocks) for tXSR because  
time is required for the completion of any internal refresh in progress.  
Upon exiting the self refresh mode, AUTO REFRESH commands must be issued at the  
specified intervals, as both SELF REFRESH and AUTO REFRESH utilize the row refresh  
counter.  
Self refresh is not supported on automotive temperature devices.  
PDF: 09005aef80725c0b  
64mb_x4x8x16_sdram.pdf - Rev. U 05/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
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© 1999 Micron Technology, Inc. All rights reserved.