128Mb: x4, x8, x16
SDRAM
1
POWER-DOWN MODE
T0
T1
T2
Tn + 1
Tn + 2
( (
) )
t
t
CK
CL
CLK
CKE
( (
t
CH
) )
t
t
CKS
CKS
( (
) )
t
t
CKS
CKH
t
t
CMS CMH
( (
) )
COMMAND
PRECHARGE
NOP
NOP
NOP
ACTIVE
( (
) )
( (
) )
( (
) )
DQM /
DQML, DQMH
( (
) )
( (
) )
A0-A9, A11
A10
ROW
ROW
ALL BANKS
( (
) )
( (
) )
SINGLE BANK
t
t
AH
AS
( (
) )
( (
) )
BA0, BA1
DQ
BANK
BANK(S)
High-Z
( (
) )
Two clock cycles
Input buffers gated off while in
power-down mode
Precharge all
active banks
All banks idle
All banks idle, enter
power-down mode
Exit power-down mode
DON’T CARE
TIMING PARAMETERS
-7E
-75
MAX
-8E
MAX UNITS
-7E
-75
-8E
SYMBOL* MIN
MAX
MIN
0.8
1.5
2.5
2.5
7.5
MIN
SYMBOL* MIN
MAX
MIN
MAX
MIN
10
1
MAX UNITS
t
t
AH
0.8
1.5
2.5
2.5
7
1
2
3
3
8
ns
ns
ns
ns
ns
CK (2)
CKH
CKS
7.5
0.8
1.5
0.8
1.5
10
0.8
1.5
0.8
1.5
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
AS
CH
2
CL
CMH
CMS
1
CK (3)
2
*CAS latency indicated in parentheses.
NOTE: 1. Violating refresh requirements during power-down may result in a loss of data.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
38
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