128Mb: x4, x8, x16
SDRAM
1
INITIALIZE AND LOAD MODE REGISTER
T0
T1
Tn + 1
To + 1
CL
Tp + 1
Tp + 2
Tp + 3
( (
) )
( (
) )
( (
) )
t
t
CK
CLK
CKE
((
))
t
( (
) )
( (
) )
( (
) )
CH
t
t
CKH
CKS
((
))
((
))
( (
) )
( (
) )
( (
) )
( (
) )
t
t
t
t
t
t
CMS CMH
CMS CMH
CMS CMH
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
AUTO
REFRESH
AUTO
REFRESH
LOAD MODE
REGISTER
COMMAND
NOP
PRECHARGE
NOP
NOP
NOP
NOP
NOP
ACTIVE
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
DQM /
DQML, DQMH
t
t
AH
AS
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
A0-A9, A11
A10
CODE
ROW
ROW
BANK
t
t
AH
AS
( (
) )
( (
) )
( (
) )
( (
) )
ALL BANKS
( (
) )
( (
) )
( (
) )
( (
) )
CODE
SINGLE BANK
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
( (
) )
ALL
BANKS
BA0, BA1
DQ
High-Z
((
))
((
))
T = 100µs
MIN
t
t
t
t
MRD
RP
RFC
RFC
Power-up:
Program Mode Register 2, 3, 4
AUTO REFRESH
VDD and
AUTO REFRESH
Precharge
all banks
CLK stable
DON’T CARE
TIMING PARAMETERS
-7E
-75
MAX
-8E
-7E
-75
MAX
-8E
SYMBOL* MIN
MAX
MIN
0.8
1.5
2.5
2.5
7.5
10
MIN
MAX UNITS
SYMBOL* MIN
MAX
MIN
MIN
2
MAX UNITS
t
t
AH
0.8
1.5
2.5
2.5
7
1
2
ns
ns
ns
ns
ns
ns
ns
CKS
CMH
CMS
MRD
RFC
RP
1.5
0.8
1.5
2
1.5
0.8
1.5
2
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
AS
1
CH
3
2
3
t
CL
3
2
CK
CK (3)
CK (2)
CKH
8
66
15
66
20
70
20
ns
ns
7.5
0.8
10
1
0.8
*CAS latency indicated in parentheses.
NOTE: 1. If CS# is HIGH at clock HIGH time, all commands applied are NOP, with CKE a “Don’t Care.”
2. The mode register may be loaded prior to the AUTO REFRESH cycles if desired.
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after command is issued.
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
37
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