欢迎访问ic37.com |
会员登录 免费注册
发布采购

MT48LC16M8A2FC-8ELIT 参数 Datasheet PDF下载

MT48LC16M8A2FC-8ELIT图片预览
型号: MT48LC16M8A2FC-8ELIT
PDF下载: 下载PDF文件 查看货源
内容描述: 同步DRAM [SYNCHRONOUS DRAM]
分类和应用: 内存集成电路动态存储器时钟
文件页数/大小: 59 页 / 1835 K
品牌: MICRON [ MICRON TECHNOLOGY ]
 浏览型号MT48LC16M8A2FC-8ELIT的Datasheet PDF文件第37页浏览型号MT48LC16M8A2FC-8ELIT的Datasheet PDF文件第38页浏览型号MT48LC16M8A2FC-8ELIT的Datasheet PDF文件第39页浏览型号MT48LC16M8A2FC-8ELIT的Datasheet PDF文件第40页浏览型号MT48LC16M8A2FC-8ELIT的Datasheet PDF文件第42页浏览型号MT48LC16M8A2FC-8ELIT的Datasheet PDF文件第43页浏览型号MT48LC16M8A2FC-8ELIT的Datasheet PDF文件第44页浏览型号MT48LC16M8A2FC-8ELIT的Datasheet PDF文件第45页  
128Mb: x4, x8, x16  
SDRAM  
SELF REFRESH MODE  
T0  
T1  
T2  
Tn + 1  
To + 1  
To + 2  
( (  
) )  
( (  
) )  
t
CL  
CLK  
CKE  
( (  
t
( (  
) )  
t
CH  
CK  
) )  
t
CKS  
RAS min1  
t
( (  
) )  
( (  
) )  
( (  
) )  
t
t
CKS  
CKH  
t
t
CMS  
CMH  
( (  
) )  
( (  
) )  
( (  
) )  
( (  
) )  
AUTO  
REFRESH  
AUTO  
REFRESH  
or COMMAND  
INHIBIT  
COMMAND  
PRECHARGE  
NOP  
NOP  
( (  
) )  
( (  
) )  
( (  
) )  
( (  
) )  
DQM/  
DQML, DQMH  
( (  
) )  
( (  
) )  
( (  
) )  
( (  
) )  
A0-A9, A11  
A10  
( (  
) )  
( (  
) )  
( (  
) )  
( (  
) )  
ALL BANKS  
SINGLE BANK  
t
t
AH  
AS  
( (  
) )  
( (  
) )  
( (  
) )  
( (  
) )  
BA0, BA1  
DQ  
BANK(S)  
High-Z  
( (  
) )  
( (  
) )  
t
t
RP  
XSR  
Precharge all  
active banks  
Enter self refresh mode  
Exit self refresh mode  
(Restart refresh time base)  
DONT CARE  
CLK stable prior to exiting  
self refresh mode  
TIMING PARAMETERS  
-7E  
-75  
MAX  
-8E  
MAX UNITS  
-7E  
MAX  
-75  
-8E  
SYMBOL* MIN  
MAX  
MIN  
0.8  
1.5  
2.5  
2.5  
7.5  
10  
MIN  
1
SYMBOL* MIN  
MIN  
1.5  
0.8  
1.5  
44  
MAX  
MIN  
2
MAX UNITS  
t
t
t
t
t
t
t
AH  
0.8  
1.5  
2.5  
2.5  
7
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CKS  
CMH  
CMS  
RAS  
RP  
1.5  
0.8  
1.5  
37  
ns  
ns  
ns  
t
t
t
t
t
t
AS  
2
1
CH  
3
2
CL  
3
120,000  
120,000  
50  
20  
80  
120,000  
ns  
ns  
ns  
CK (3)  
CK (2)  
CKH  
8
15  
20  
7.5  
0.8  
10  
1
XSR  
75  
75  
0.8  
*CAS latency indicated in parentheses.  
NOTES:1. No maximum time limit for Self Refresh. tRAS max applies to non-Self Refresh mode.  
t
2. XSR requires minimum of two clocks regardless of frequency or timing.  
128Mb: x4, x8, x16 SDRAM  
128MSDRAM_E.p65 Rev. E; Pub. 1/02  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2001, Micron Technology, Inc.  
41  
 复制成功!