128Mb: x4, x8, x16
SDRAM
1
READ – WITHOUT AUTO PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
t
CH
t
t
CKS
CKH
CKE
t
t
CMS CMH
COMMAND
ACTIVE
NOP
READ
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
ROW
t
t
CMS CMH
DQM /
DQML, DQMH
t
t
AS
AH
COLUMN m2
A0-A9, A11
ROW
t
t
AS
AH
ALL BANKS
ROW
ROW
A10
SINGLE BANKS
BANK(S)
DISABLE AUTO PRECHARGE
BANK
t
t
AS
AH
BA0, BA1
BANK
BANK
t
t
t
AC
AC
AC
t
t
t
t
t
OH
AC
OH
OH
OH
DOUT
m
D
OUT m+1
D
OUT m+2
DOUT m+3
DQ
t
LZ
t
HZ
t
t
RCD
CAS Latency
RP
t
RAS
t
RC
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-7E
-75
-8E
MAX UNITS
-7E
-75
-8E
SYMBOL* MIN
MAX
5.4
MIN
MAX
5.4
6
MIN
SYMBOL* MIN
MAX
MIN
MAX
MIN
MAX UNITS
t
t
AC(3)
6
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMH
CMS
HZ(3)
HZ(2)
LZ
0.8
1.5
0.8
1.5
1
2
ns
ns
t
t
t
t
t
t
t
t
t
t
AC(2)
5.4
t
AH
0.8
1.5
2.5
2.5
7
0.8
1.5
2.5
2.5
7.5
10
1
2
5.4
5.4
5.4
6
6
6
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
AS
CH
3
1
1
1
CL
3
OH
3
3
3
CK(3)
CK(2)
CKH
CKS
8
RAS
RC
37
60
15
15
120,000
44
66
20
20
120,000
50
70
20
20
120,000
7.5
0.8
1.5
10
1
0.8
1.5
RCD
RP
2
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual”
PRECHARGE.
2. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”
128Mb: x4, x8, x16 SDRAM
128MSDRAM_E.p65 – Rev. E; Pub. 1/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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