欢迎访问ic37.com |
会员登录 免费注册
发布采购

MT48LC2M32B2TG 参数 Datasheet PDF下载

MT48LC2M32B2TG图片预览
型号: MT48LC2M32B2TG
PDF下载: 下载PDF文件 查看货源
内容描述: 同步DRAM [SYNCHRONOUS DRAM]
分类和应用: 动态存储器
文件页数/大小: 53 页 / 1810 K
品牌: MICRON [ MICRON TECHNOLOGY ]
 浏览型号MT48LC2M32B2TG的Datasheet PDF文件第5页浏览型号MT48LC2M32B2TG的Datasheet PDF文件第6页浏览型号MT48LC2M32B2TG的Datasheet PDF文件第7页浏览型号MT48LC2M32B2TG的Datasheet PDF文件第8页浏览型号MT48LC2M32B2TG的Datasheet PDF文件第10页浏览型号MT48LC2M32B2TG的Datasheet PDF文件第11页浏览型号MT48LC2M32B2TG的Datasheet PDF文件第12页浏览型号MT48LC2M32B2TG的Datasheet PDF文件第13页  
64Mb: x32  
SDRAM  
Commands  
Truth Table 1 provides a quick reference of avail-  
able commands. This is followed by a written descrip-  
tion of each command. Three additional Truth Tables  
appear following the Operation section; these tables  
provide current state/next state information.  
TRUTH TABLE 1 – COMMANDS AND DQM OPERATION  
(Note: 1)  
NAME (FUNCTION)  
CS# RAS# CAS# WE# DQM  
ADDR  
DQs NOTES  
COMMAND INHIBIT (NOP)  
H
L
L
L
L
L
L
L
X
H
L
X
H
H
L
X
H
H
H
L
X
X
X
X
X
X
X
NO OPERATION (NOP)  
ACTIVE (Select bank and activate row)  
READ (Select bank and column, and start READ burst)  
WRITE (Select bank and column, and start WRITE burst)  
BURST TERMINATE  
Bank/Row  
X
X
3
4
4
H
H
H
L
L/H8 Bank/Col  
L/H8 Bank/Col  
L
Valid  
Active  
X
H
H
L
L
X
X
X
X
Code  
X
PRECHARGE (Deactivate row in bank or banks)  
L
5
AUTO REFRESH or SELF REFRESH  
(Enter self refresh mode)  
L
H
X
6, 7  
LOAD MODE REGISTER  
L
L
L
L
X
L
Op-Code  
X
2
8
8
Write Enable/Output Enable  
Write Inhibit/Output High-Z  
Active  
High-Z  
H
NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.  
2. A0-A10 define the op-code written to the Mode Register.  
3. A0-A10 provide row address, BA0 and BA1 determine which bank is made active.  
4. A0-A7 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while  
A10 LOW disables the auto precharge feature; BA0 and BA1 determine which bank is being read from  
or written to.  
5. A10 LOW: BA0 and BA1 determine the bank being precharged. A10 HIGH: All banks precharged and  
BA0 and BA1 are “Don’t Care.”  
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.  
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.  
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). DQM0  
controls DQ0-DQ7; DQM1 controls DQ8-DQ15; DQM2 controls DQ16-DQ23; and DQM3 controls  
DQ24-DQ31.  
64Mb: x32 SDRAM  
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02  
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.  
©2002,MicronTechnology,Inc.  
9
 复制成功!