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MT48LC2M32B2TG 参数 Datasheet PDF下载

MT48LC2M32B2TG图片预览
型号: MT48LC2M32B2TG
PDF下载: 下载PDF文件 查看货源
内容描述: 同步DRAM [SYNCHRONOUS DRAM]
分类和应用: 动态存储器
文件页数/大小: 53 页 / 1810 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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64Mb: x32  
SDRAM  
READs  
READ bursts are initiated with a READ command,  
as shown in Figure 5.  
Upon completion of a burst, assuming no other com-  
mands have been initiated, the DQs will go High-Z. A  
full-page burst will continue until terminated. (At the  
end of the page, it will wrap to column 0 and continue.)  
Data from any READ burst may be truncated with a  
subsequent READ command, and data from a fixed-  
length READ burst may be immediately followed by  
data from a READ command. In either case, a continu-  
ous flow of data can be maintained. The first data ele-  
ment from the new burst follows either the last ele-  
ment of a completed burst or the last desired data ele-  
ment of a longer burst that is being truncated. The new  
READ command should be issued x cycles before the  
clock edge at which the last desired data element is  
valid, where x equals the CAS latency minus one. This  
is shown in Figure 7 for CAS latencies of one, two and  
The starting column and bank addresses are pro-  
vided with the READ command, and auto precharge is  
either enabled or disabled for that burst access. If auto  
precharge is enabled, the row being accessed is  
precharged at the completion of the burst. For the ge-  
neric READ commands used in the following illustra-  
tions, auto precharge is disabled.  
During READ bursts, the valid data-out element  
from the starting column address will be available fol-  
lowing the CAS latency after the READ command. Each  
subsequent data-out element will be valid by the next  
positive clock edge. Figure 6 shows general timing for  
each possible CAS latency setting.  
Figure 6  
Figure 5  
CAS Latency  
READ Command  
T0  
T1  
T2  
CLK  
CLK  
COMMAND  
CKE  
CS#  
HIGH  
READ  
NOP  
t
t
LZ  
OH  
DOUT  
DQ  
t
AC  
CAS Latency = 1  
RAS#  
T0  
T1  
T2  
T3  
CAS#  
WE#  
CLK  
COMMAND  
READ  
NOP  
t
NOP  
t
LZ  
OH  
DOUT  
DQ  
t
COLUMN  
ADDRESS  
AC  
A0–A7  
A8, A9  
CAS Latency = 2  
ENABLE AUTO PRECHARGE  
DISABLE AUTO PRECHARGE  
T0  
T1  
T2  
T3  
T4  
A10  
CLK  
COMMAND  
READ  
NOP  
NOP  
NOP  
t
t
BANK  
ADDRESS  
LZ  
OH  
BA0, 1  
DOUT  
DQ  
t
AC  
CAS Latency = 3  
DON’T CARE  
UNDEFINED  
64Mb: x32 SDRAM  
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02  
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.  
©2002,MicronTechnology,Inc.  
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