64Mb: x32
SDRAM
Operation
Figure 3
Activating a Specific Row in a
Specific Bank
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be is-
sued to a bank within the SDRAM, a row in that bank
must be “opened.” This is accomplished via the AC-
TIVE command, which selects both the bank and the
row to be activated. See Figure 3.
CLK
After opening a row (issuing an ACTIVE command),
a READ or WRITE command may be issued to that row,
CKE
CS#
HIGH
t
t
subject to the RCD specification. RCD (MIN) should
be divided by the clock period and rounded up to the
next whole number to determine the earliest clock edge
after the ACTIVE command on which a READ or WRITE
t
command can be issued. For example, a RCD specifi-
RAS#
cation of 20ns with a 125 MHz clock (8ns period) results
in 2.5 clocks, rounded to 3. This is reflected in Figure 4,
t
which covers any case where 2 < RCD (MIN)/tCK - 3.
CAS#
WE#
(The same procedure is used to convert other specifi-
cation limits from time units to clock cycles.)
A subsequent ACTIVE command to a different row
in the same bank can only be issued after the previous
active row has been “closed” (precharged). The mini-
mum time interval between successive ACTIVE com-
ROW
ADDRESS
A0–A10
t
mands to the same bank is defined by RC.
A subsequent ACTIVE command to another bank
can be issued while the first bank is being accessed,
which results in a reduction of total row-access over-
head. The minimum time interval between successive
ACTIVE commands to different banks is defined by
tRRD.
BANK
ADDRESS
BA0, BA1
Figure 4
Example: Meeting RCD (MIN) When 2 < RCD (MIN)/ CK - 3
t
t
t
T0
T1
T2
T3
CLK
t
t
t
CK
CK
CK
READ or
WRITE
COMMAND
ACTIVE
NOP
NOP
t
RCD (MIN)
t
t
RCD (MIN) +0.5 CK
t
t
t
RCD (MIN) = 20ns, CK = 8ns
RCD (MIN) x CK
DON’T CARE
t
where x = number of clocks for equation to be true.
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
12
MICRON [ MICRON TECHNOLOGY ]
