64Mb: x32
SDRAM
PINDESCRIPTIONS
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
68
CLK
Input Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal burst
counterandcontrolstheoutputregisters.
67
CKE
Input ClockEnable:CKEactivates(HIGH)anddeactivates(LOW)theCLKsignal.
DeactivatingtheclockprovidesPRECHARGEPOWER-DOWNandSELFREFRESH
operation(allbanksidle),ACTIVEPOWER-DOWN(rowactiveinanybank)or
CLOCKSUSPENDoperation(burst/accessinprogress).CKEissynchronous
exceptafterthedeviceenterspower-downandselfrefreshmodes,where
CKEbecomesasynchronousuntilafterexitingthesamemode.Theinput
buffers,includingCLK,aredisabledduringpower-downandselfrefresh
modes,providinglowstandbypower.CKEmaybetiedHIGH.
20
CS#
Input ChipSelect:CS#enables(registeredLOW)anddisables(registeredHIGH)the
commanddecoder.AllcommandsaremaskedwhenCS#isregisteredHIGH.
CS#providesforexternalbankselectiononsystemswithmultiplebanks.
CS#isconsideredpartofthecommandcode.
17, 18, 19
WE#,CAS#, Input CommandInputs:WE#,CAS#,andRAS#(alongwithCS#)definethe
RAS#
commandbeingentered.
16, 71, 28, 59
DQM0-
DQM3
Input Input/OutputMask:DQMissampledHIGHandisaninputmasksignal
for write accesses and an output enable signal for read accesses. Input data
ismaskedduringaWRITEcycle. TheoutputbuffersareplacedinaHigh-Z
state(two-clocklatency)duringaREADcycle.DQM0correspondstoDQ0-
DQ7;DQM1correspondstoDQ8-DQ15;DQM2correspondstoDQ16-DQ23;
andDQM3correspondstoDQ24-DQ31.DQM0-DQM3areconsideredsame
statewhenreferencedasDQM.
22, 23
BA0,BA1
A0-A10
Input BankAddressInput(s):BA0andBA1definetowhichbanktheACTIVE,READ,
WRITEorPRECHARGEcommandisbeingapplied.
25-27, 60-66, 24
Input AddressInputs:A0-A10aresampledduringtheACTIVEcommand(row-
addressA0-A10)andREAD/WRITEcommand(column-addressA0-A7withA10
definingautoprecharge)toselectonelocationoutofthememoryarrayin
therespectivebank.A10issampledduringaPRECHARGEcommandto
determineifallbanksaretobeprecharged(A10HIGH)orbankselectedby
BA0,BA1(LOW).Theaddressinputsalsoprovidetheop-codeduringaLOAD
MODEREGISTERcommand.
2, 4, 5, 7, 8, 10, 11, 13,
74, 76, 77, 79, 80, 82, 83,
85, 31, 33, 34, 36, 37, 39,
40, 42, 45, 47, 48, 50, 51,
53, 54, 56
DQ0-DQ31 Input/ Data I/Os: Data bus.
Output
14, 21, 30, 57, 69, 70, 73
NC
–
NoConnect:Thesepinsshouldbeleftunconnected.Pin70isreserved
forSSTLreferencevoltagesupply.
3, 9, 35, 41, 49, 55, 75, 81
6, 12, 32, 38, 46, 52, 78, 84
1, 15, 29, 43
V
DD
Q
Supply DQ PowerSupply: Isolatedonthedieforimprovednoiseimmunity.
Supply DQ Ground:ProvideisolatedgroundtoDQsforimprovednoiseimmunity.
Supply PowerSupply:+3.3V 0.3V. (Seenote27onpage35.)
Supply Ground.
V
SS
Q
V
DD
44, 58, 72, 86
V
SS
64Mb: x32 SDRAM
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
5
©2002,MicronTechnology,Inc.
MICRON [ MICRON TECHNOLOGY ]
