64Mb: x32
SDRAM
Burst Type
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is deter-
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 1.
Table 1
Burst Definition
Burst Starting Column Order of Accesses Within a Burst
Length
Address
Type = Sequential Type = Interleaved
A0
0
1
A1 A0
0
0
0
1
1
0
1
1
A2 A1 A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1
1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not Supported
2
Figure 1
Mode Register Definition
4
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
10
9
8
7
6
5
4
BT
3
2
1
0
Mode Register (Mx)
Reserved* WB Op Mode CAS Latency
Burst length
1. *Should program
A10, BA0, and BA1= “0”
to ensure compatibility
with future device
M2 M1 M0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
8
Burst Length
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
Full
Page
(256)
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn + 1, Cn + 2
n = A0-A7
Cn + 3, Cn + 4...
…Cn - 1,
(Location 0 -256)
Cn…
NOTE:
M3
0
1
Burst Type
Sequential
Interleave
M6 M5 M4
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
CAS Latency
Reserved
1
2
3
Reserved
Reserved
Reserved
Reserved
1. For a burst length of two, A1-A7 select the block-
of-two burst; A0 selects the starting column
within the block.
2. For a burst length of four, A2-A7 select the block-
of-four burst; A0-A1 select the starting column
within the block.
3. For a burst length of eight, A3-A7 select the block-
of-eight burst; A0-A2 select the starting column
within the block.
4. For a full-page burst, the full row is selected and
A0-A7 select the starting column.
5. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
6. For a burst length of one, A0-A7 select the unique
column to be accessed, and mode register bit M3
is ignored.
M8
0
-
M7
0
-
M6 - M0
Defined
-
Operating Mode
Standard operation
All other states reserved
M9
0
1
Write Burst Mode
Programmed Burst Length
Single Location Access
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
MICRON [ MICRON TECHNOLOGY ]
