欢迎访问ic37.com |
会员登录 免费注册
发布采购

MT48LC2M32B2TG 参数 Datasheet PDF下载

MT48LC2M32B2TG图片预览
型号: MT48LC2M32B2TG
PDF下载: 下载PDF文件 查看货源
内容描述: 同步DRAM [SYNCHRONOUS DRAM]
分类和应用: 动态存储器
文件页数/大小: 53 页 / 1810 K
品牌: MICRON [ MICRON TECHNOLOGY ]
 浏览型号MT48LC2M32B2TG的Datasheet PDF文件第2页浏览型号MT48LC2M32B2TG的Datasheet PDF文件第3页浏览型号MT48LC2M32B2TG的Datasheet PDF文件第4页浏览型号MT48LC2M32B2TG的Datasheet PDF文件第5页浏览型号MT48LC2M32B2TG的Datasheet PDF文件第6页浏览型号MT48LC2M32B2TG的Datasheet PDF文件第7页浏览型号MT48LC2M32B2TG的Datasheet PDF文件第8页浏览型号MT48LC2M32B2TG的Datasheet PDF文件第9页  
64Mb: x32
SDRAM
SYNCHRONOUS
DRAM
FEATURES
• PC100 functionality
• Fully synchronous; all signals registered on
positive edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 4,096-cycle refresh (15.6µs/row)
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
• Supports CAS latency of 1, 2, and 3
MT48LC2M32B2 - 512K x 32 x 4 banks
For the latest data sheet, please refer to the Micron Web
site:
PIN ASSIGNMENT (TOP VIEW)
86-PIN TSOP
V
DD
DQ0
V
DD
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
DD
Q
DQ5
DQ6
V
SS
Q
DQ7
NC
V
DD
DQM0
WE#
CAS#
RAS#
CS#
NC
BA0
BA1
A10
A0
A1
A2
DQM2
V
DD
NC
DQ16
V
SS
Q
DQ17
DQ18
V
DD
Q
DQ19
DQ20
V
SS
Q
DQ21
DQ22
V
DD
Q
DQ23
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
OPTIONS
• Configuration
2 Meg x 32 (512K x 32 x 4 banks)
• Plastic Package - OCPL
1
86-pin TSOP (400 mil)
• Timing (Cycle Time)
5ns (200 MHz)
5.5ns (183 MHz)
6ns (166 MHz)
7ns (143 MHz)
• Operating Temperature Range
Commercial (0° to +70°C)
Extended (-40°C to +85°C)
NOTE:
1. Off-center parting line
2. Available on -7
Part Number Example:
MARKING
2M32B2
TG
-5
-55
-6
-7
None
IT
2
MT48LC2M32B2TG-7
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
DD
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
DD
Q
DQ8
NC
V
SS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
SS
NC
DQ31
V
DD
Q
DQ30
DQ29
V
SS
Q
DQ28
DQ27
V
DD
Q
DQ26
DQ25
V
SS
Q
DQ24
V
SS
KEY TIMING PARAMETERS
SPEED
GRADE
-5
-55
-6
-7
CLOCK
ACCESS TIME
FREQUENCY
CL = 3*
200 MHz
183 MHz
166 MHz
143 MHz
4.5ns
5ns
5.5ns
5.5ns
SETUP
TIME
1.5ns
1.5ns
1.5ns
2ns
HOLD
TIME
1ns
1ns
1ns
1ns
Note:
The # symbol indicates signal is active LOW.
2 Meg x 32
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
512K x 32 x 4 banks
4K
2K (A0-A10)
4 (BA0, BA1)
256 (A0-A7)
*CL = CAS (READ) latency
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.