64Mb: x32
SDRAM
three; data element
n
+ 3 is either the last of a burst of
four or the last desired of a longer burst. This 64Mb
SDRAM uses a pipelined architecture and therefore
does not require the 2n rule associated with a prefetch
architecture. A READ command can be initiated on any
clock cycle following a previous READ command. Full-
speed random read accesses can be performed to the
same bank, as shown in Figure 8, or each subsequent
READ may be performed to a different bank.
Figure 7
Consecutive READ Bursts
T0
CLK
T1
T2
T3
T4
T5
COMMAND
READ
NOP
NOP
NOP
READ
X
= 0 cycles
NOP
ADDRESS
BANK,
COL
n
BANK,
COL
b
DQ
D
OUT
n
D
OUT
n
+1
D
OUT
n
+2
D
OUT
n
+3
D
OUT
b
CAS Latency = 1
T0
CLK
T1
T2
T3
T4
T5
T6
COMMAND
READ
NOP
NOP
NOP
READ
NOP
NOP
X
= 1 cycle
ADDRESS
BANK,
COL
n
BANK,
COL
b
DQ
CAS Latency = 2
D
OUT
n
D
OUT
n
+1
D
OUT
n
+2
D
OUT
n
+3
D
OUT
b
T0
CLK
T1
T2
T3
T4
T5
T6
T7
COMMAND
READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
X
= 2 cycles
ADDRESS
BANK,
COL n
BANK,
COL
b
DQ
CAS Latency = 3
D
OUT
n
D
OUT
n
+1
D
OUT
n
+2
D
OUT
n
+3
D
OUT
b
NOTE:
Each READ command may be to either bank. DQM is LOW.
DON’T CARE
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
MICRON [ MICRON TECHNOLOGY ]
