64Mb: x32
SDRAM
A fixed-length READ burst may be followed by, or
truncated with, a PRECHARGE command to the same
bank (provided that auto precharge was not acti-
vated), and a full-page burst may be truncated with a
PRECHARGE command to the same bank. The
PRECHARGE command should be issued
x
cycles be-
fore the clock edge at which the last desired data ele-
ment is valid, where
x
equals the CAS latency minus
one. This is shown in Figure 11 for each possible CAS
latency; data element
n
+ 3 is either the last of a burst of
four or the last desired of a longer burst. Following the
PRECHARGE command, a subsequent command to
the same bank cannot be issued until
t
RP is met. Note
that part of the row precharge time is hidden during
the access of the last data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
Figure 11
READ to PRECHARGE
T0
CLK
t RP
T1
T2
T3
T4
T5
T6
T7
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
X
= 0 cycles
NOP
NOP
ACTIVE
ADDRESS
BANK
a,
COL
n
BANK
(a or all)
BANK
a,
ROW
DQ
CAS Latency = 1
D
OUT
n
D
OUT
n
+1
D
OUT
n
+2
D
OUT
n
+3
T0
CLK
T1
T2
T3
T4
T5
T6
T7
t RP
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
X
= 1 cycle
NOP
NOP
ACTIVE
ADDRESS
BANK
a,
COL
n
BANK
(a or all)
BANK
a,
ROW
DQ
CAS Latency = 2
D
OUT
n
D
OUT
n
+1
D
OUT
n
+2
D
OUT
n
+3
T0
CLK
T1
T2
T3
T4
T5
T6
T7
t RP
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
X
= 2 cycles
ADDRESS
BANK
a,
COL
n
BANK
(a or all)
BANK
a,
ROW
DQ
CAS Latency = 3
D
OUT
n
D
OUT
n
+1
D
OUT
n
+2
D
OUT
n
+3
NOTE:
DQM is LOW.
DON’T CARE
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
17
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
MICRON [ MICRON TECHNOLOGY ]
