512Mb : 32 Me g x 16, 16 Me g x 32 Mo b ile SDRAM
Re g ist e r De fin it io n
Fig u re 6:
Mo d e Re g ist e r De fin it io n
A12
BA1 BA0
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
M12
M14 M13
M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0
0
14 13 12 11 10
9
8
7
6
5
4
3
2
1
Mode
Register (Mx)
1
0
0
Reserved
WB Op Mode CAS Latency BT Burst Length
Burst Length
Mode Register Definition
Base mode register
Reserved
M13
M14
0
1
0
1
0
0
1
1
M2 M1 M0
M3 = 0
M3 = 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
Extended mode register
Reserved
2
2
4
4
8
8
M9
0
Write Burst Mode
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Programmed burst length
1
Single location access
M8 M7 Operating Mode
Normal operation
0
–
0
–
All other states reserved
Burst Type
Sequential
Interleaved
M3
0
1
CAS Latency
M6 M5 M4
Reserved
Reserved
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3
Reserved
Reserved
Reserved
Reserved
Notes: 1. Should be programmed to “0” to ensure compatibility with future devices.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
14
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