512Mb : 32 Me g x 16, 16 Me g x 32 Mo b ile SDRAM
Re g ist e r De fin it io n
Fig u re 8:
EMR De fin it io n
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0
0
14 13 12 11 10
9
8
7
6
5
4
3
2
1
Extended Mode
Register
1
1
0
set to “0”
DS
TCSR
PASR
Mode Register Definintion
Standard mode register
Reserved
Extended mode register
Reserved
Driver Strength
E13
0
E14
0
E6 E5
Full-strength driver
0
0
1
1
0
1
0
1
1
0
Half-strength driver
0
1
Quarter-strength driver
1
1
One eighth-strength driver
E12 E11 E10 E9 E8 E7
E2 E1 E0 Partial-Array Self Refresh Coverage
Normal operation
0
–
0
–
0
–
0
–
0
–
0
–
0
0
0
0
0
1
0
1
0
Full array
All other states reserved
Half array
Quarter array
0
1
1
1
1
0
0
1
1
0
1
0
Reserved
Reserved
One-eighth array
One-sixteenth array
1
1
1
Reserved
Notes: 1. On-die temperature sensor is used in place of TCSR. Setting these bits will have no effect.
The extended mode register must be programmed with E7 through E12 set to “0.” It
must be loaded when all banks are idle and no bursts are in progress, and the controller
must wait the specified time before initiating any subsequent operation. Violating either
of these requirements results in unspecified operation. Once the values are entered, the
extended mode register settings will be retained even after exiting deep power-down
mode.
Te m p e ra t u re -Co m p e n sa t e d Se lf Re fre sh (TCSR)
On this version of the Mobile DDR SDRAM, a temperature sensor is implemented for
automatic control of the self refresh oscillator. Programming of the TCSR bits will have
no effect on the device. The self refresh oscillator will continue refresh at the factory
programmed optimal rate for the device temperature.
Pa rt ia l-Arra y Se lf Re fre sh (PASR)
For further power savings during self refresh, the partial-array self refresh (PASR) feature
allows the controller to select the amount of memory that will be refreshed during self
refresh. The following refresh options are available.
1. All banks (banks 0, 1, 2, and 3).
2. Two banks (banks 0 and 1; BA1=0).
3. One bank (bank 0; BA1 = BA0 = 0).
4. Half bank (bank 0; BA1 = BA0 = row address MSB = 0).
5. Quarter bank (bank 0; BA1 = BA0; row address MSB = row address MSB - 1 = 0).
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
17
©2005 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
