1Gb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Figure 29: Nominal Slew Rate for tDH
1
DQS
1
DQS#
t
t
t
t
IS
IH
IH
IS
VDDQ
VIH(AC)min
VIH(DC)min
DC to V
REF
region
Nominal
slew rate
VREF(DC)
Nominal
slew rate
DC to V
region
REF
VIL(DC)max
VIL(AC)max
VSS
ΔTF
ΔTR
Hold slew rate
VREF(DC)
-
Δ
VIL(DC)max
TR
VIH(DC)min
-
VREF(DC)
Hold slew rate
rising signal
=
=
falling signal
Δ
TF
1. DQS, DQS# signals must be monotonic between VIL(DC)max and VIH(DC)min
.
Note:
Figure 30: Tangent Line for tDH
1
DQS
1
DQS#
t
t
t
t
IS
IH
IH
IS
VDDQ
VIH(AC)min
Nominal
line
VIH(DC)min
DC to V
REF
region
Tangent
line
VREF(DC)
Tangent
line
DC to V
region
REF
Nominal
line
VIL(DC)max
VIL(AC)max
VSS
ΔTF
ΔTR
Tangent line (V
- V
)
Tangent line (V
- V
)
REF[DC]
REF[DC]
IL[DC]max
IH[DC]min
Hold slew rate
rising signal
Hold slew rate
falling signal
=
=
ΔTR
ΔTF
1. DQS, DQS# signals must be monotonic between VIL(DC)max and VIH(DC)min
.
Note:
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
65
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