1Gb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Figure 27: Nominal Slew Rate for tDS
1
DQS
1
DQS#
t
t
t
DS
t
DH
DH
DS
VDDQ
VIH(AC)min
V
to AC
region
REF
VIH(DC)min
Nominal
slew rate
VREF(DC)
Nominal
slew rate
VIL(DC)max
V
to AC
region
REF
VIL(AC)max
VSS
ΔTF
ΔTR
V
REF(DC) - VIL(AC)max
VIH(AC)min
-
VREF(DC)
Setup slew rate
falling signal
Setup slew rate
rising signal
=
=
ΔTF
ΔTR
1. DQS, DQS# signals must be monotonic between VIL(DC)max and VIH(DC)min
.
Note:
Figure 28: Tangent Line for tDS
1
DQS
1
DQS#
t
t
t
DS
t
DS
DH
DH
V
DDQ
V
V
IH(AC)min
Nominal
line
V
to AC
REF
region
IH(DC)min
Tangent line
V
REF(DC)
Tangent line
V
V
IL(DC)max
IL(AC)max
Nominal line
V
to AC
region
REF
ΔTR
ΔTF
V
SS
Tangent line (V
- V )
IL[AC]max
Tangent line (V
- V )
REF[DC]
REF[DC]
IH[AC]min
Setup slew rate
falling signal
Setup slew rate
rising signal
=
=
ΔTF
ΔTR
1. DQS, DQS# signals must be monotonic between VIL(DC)max and VIH(DC)min
.
Note:
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
64
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