1Gb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Figure 31: AC Input Test Signal Waveform Command/Address Balls
CK#
CK
t
t
t
t
IH
IS
IH
b
IS
b
b
b
Logic levels
VDDQ
VIH(AC)min
VIH(DC)min
VREF(DC)
VIL(DC)min
VIL(AC)min
VSSQ
VREF levels
t
t
IH
t
t
IH
IS
a
IS
a
a
a
Figure 32: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential)
DQS#
DQS
t
t
t
t
DH
DS
DH
DS
b
b
b
b
Logic levels
VDDQ
VIH(AC)min
VIH(DC)min
VREF(DC)
VIL(DC)max
VIL(AC)max
VSSQ
VREF levels
t
t
t
DS
a
t
DH
a
DS
DH
a
a
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
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66
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