1Gb: x4, x8, x16 DDR3 SDRAM
ODT Characteristics
Figure 24: ODT Timing Reference Load
VDDQ/2
V
DUT
REF
RTT = 25ȍ
DQ, DM
DQS, DQS#
CK, CK#
VTT = VSSQ
TDQS, TDQS#
Timing reference point
RZQ = 240ȍ
ZQ
VSSQ
Table 35: ODT Timing Definitions
Symbol
Begin Point Definition
End Point Definition
Figure
tAON
Rising edge of CK - CK# defined by the end Extrapolated point at VSSQ
point of ODTLon
Figure 25 (page 61)
tAOF
Rising edge of CK - CK# defined by the end Extrapolated point at VRTT,nom
point of ODTLoff
Figure 25 (page 61)
Figure 26 (page 61)
Figure 26 (page 61)
Figure 27 (page 62)
tAONPD Rising edge of CK - CK# with ODT first being Extrapolated point at VSSQ
registered HIGH
tAOFPD Rising edge of CK - CK# with ODT first being Extrapolated point at VRTT,nom
registered LOW
tADC
Rising edge of CK - CK# defined by the end Extrapolated points at VRTT(WR) and
point of ODTLcnw, ODTLcwn4, or ODTLcwn8 VRTT,nom
Table 36: Reference Settings for ODT Timing Measurements
Measured Parameter
RTT,nom Setting
RZQ/4 (60Ωꢀ
RZQ/12 (20Ωꢀ
RZQ/4 (60Ωꢀ
RZQ/12 (20Ωꢀ
RZQ/4 (60Ωꢀ
RZQ/12 (20Ωꢀ
RZQ/4 (60Ωꢀ
RZQ/12 (20Ωꢀ
RZQ/12 (20Ωꢀ
RTT(WR) Setting
VSW1
50mV
VSW2
tAON
n/a
100mV
200mV
100mV
200mV
100mV
200mV
100mV
200mV
300mV
n/a
100mV
50mV
tAOF
tAONPD
tAOFPD
tADC
n/a
n/a
100mV
50mV
n/a
n/a
n/a
100mV
50mV
n/a
100mV
200mV
RZQ/2 (120Ωꢀ
1. Assume an RZQ of 240Ω ( 1%) and that proper ZQ calibration has been performed at a
Note:
stable temperature and voltage (VDDQ = VDD, VSSQ = VSS).
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
60
2006 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
