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MT41J256M4 参数 Datasheet PDF下载

MT41J256M4图片预览
型号: MT41J256M4
PDF下载: 下载PDF文件 查看货源
内容描述: DDR3 SDRAM MT41J256M4 â ????梅格32 ×4× 8银行MT41J128M8 â ????梅格16 ×8× 8银行MT41J64M16 â ???? 8梅格×16× 8银行 [DDR3 SDRAM MT41J256M4 – 32 Meg x 4 x 8 banks MT41J128M8 – 16 Meg x 8 x 8 banks MT41J64M16 – 8 Meg x 16 x 8 banks]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 214 页 / 2938 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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Figure 71: Nonconsecutive READ Bursts  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
T9  
T10  
T11  
T12  
T13  
T14  
T15  
T16  
T17  
CK#  
CK  
Command  
READ  
NOP  
NOP  
NOP  
NOP  
READ  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
Bank a,  
Col n  
Bank a,  
Col b  
Address  
CL = 8  
CL = 8  
DQS, DQS#  
DQ  
DO  
n
DO  
b
Transitioning Data  
Don’t Care  
1. AL = 0, RL = 8.  
2. DO n (or b) = data-out from column n (or column b).  
Notes:  
3. Seven subsequent elements of data-out appear in the programmed order following DO n.  
4. Seven subsequent elements of data-out appear in the programmed order following DO b.  
Figure 72: READ (BL8) to WRITE (BL8)  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
T9  
T10  
T11  
T12  
T13  
T14  
T15  
CK#  
CK  
1
READ  
NOP  
NOP  
NOP  
NOP  
NOP  
WRITE  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
NOP  
Command  
t
t
WR  
t
t
t
READ-to-WRITE command delay = RL + CCD + 2 CK - WL  
BL = 4 clocks  
WR  
Bank,  
Col n  
Bank,  
Col b  
2
Address  
t
t
t
t
RPRE  
RPST  
WPRE  
WPST  
DQS, DQS#  
DO  
n
DO  
DO  
DO  
DO  
DO  
DO  
DO  
DI  
n
DI  
DI  
DI  
DI  
DI  
DI  
DI  
3
DQ  
n + 1  
n + 2 n + 3 n + 4 n + 5  
n + 6 n + 7  
WL = 5  
n + 1 n + 2 n + 3  
n + 4 n + 5 n + 6 n + 7  
RL = 5  
Transitioning Data  
Don’t Care  
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.  
Notes:  
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the READ command at  
T0, and the WRITE command at T6.  
3. DO n = data-out from column, DI b = data-in for column b.  
4. BL8, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).  
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