256Mb, 3V Multiple I/O Serial Flash Memory
CLEAR FLAG STATUS REGISTER Operation
CLEAR FLAG STATUS REGISTER Operation
To initiate a command, S# is driven LOW. For the extended-, dual-, and quad-SPI proto-
cols respectively, input is on DQ0, DQ[1:0], and DQ[3:0]. The operation is terminated by
driving S# HIGH at any time.
Table 27: CLEAR FLAG STATUS REGISTER Operation
Operation Name
Description/Conditions
CLEAR FLAG STATUS
REGISTER (50h)
Resets the error bits (erase, program, and protection)
Figure 34: CLEAR FLAG STATUS REGISTER Timing
Extended
0
7
C
LSB
DQ0
Command
0
MSB
Dual
3
C
LSB
DQ[1:0]
Command
0
MSB
MSB
Quad
1
C
LSB
DQ[3:0]
Command
1. S# not shown.
Note:
CCMTD-1725822587-3368
mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN
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