256Mb, 3V Multiple I/O Serial Flash Memory
WRITE REGISTER Operations
2. A READ NONVOLATILE CONFIGURATION REGISTER operation will output data starting
from the least significant byte.
3. S# not shown.
WRITE REGISTER Operations
Before a WRITE REGISTER command is initiated, the WRITE ENABLE command must
be executed to set the write enable latch bit to 1. To initiate a command, S# is driven
LOW and held LOW until the eighth bit of the last data byte has been latched in, after
which it must be driven HIGH; for the WRITE NONVOLATILE CONFIGURATION REG-
ISTER command, S# is held LOW until the 16th bit of the last data byte has been latched
in. For the extended, dual, and quad SPI protocols respectively, input is on DQ0,
DQ[1:0], and DQ[3:0], followed by the data bytes. If S# is not driven HIGH, the com-
mand is not executed, flag status register error bits are not set, and the write enable
latch remains set to 1. The operation is self-timed and its duration is tW for WRITE STA-
TUS REGISTER and tNVCR for WRITE NONVOLATILE CONFIGURATION REGISTER.
Table 26: WRITE REGISTER Operations
Operation Name
Description/Conditions
Note
WRITE STATUS REGISTER (01h)
The WRITE STATUS REGISTER command writes new values to status
register bits 7:2, enabling software data protection. The status reg-
ister can also be combined with the W# signal to provide hardware
data protection. This command has no effect on status register bits
1:0.
1
For the WRITE STATUS REGISTER and WRITE NONVOLATILE CONFIG-
URATION REGISTER commands, when the operation is in progress,
the write in progress bit is set to 1. The write enable latch bit is
cleared to 0, whether the operation is successful or not. The status
register and flag status register can be polled for the operation sta-
tus. When the operation completes, the write in progress bit is
cleared to 0, whether the operation is successful or not.
WRITE NONVOLATILE CONFIGURATION
REGISTER (B1h)
WRITE VOLATILE CONFIGURATION REGIS- Because register bits are volatile, change to the bits is immediate.
TER (81h)
Reserved bits are not affected by this command.
WRITE ENHANCED VOLATILE CONFIGURA-
TION REGISTER (61h)
WRITE EXTENDED ADDRESS REGISTER
(C5h)
1. The WRITE NONVOLATILE CONFIGURATION REGISTER operation must have input data
starting from the least significant byte.
Note:
CCMTD-1725822587-3368
mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN
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