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MT250QL01GABA8ESF0AITES 参数 Datasheet PDF下载

MT250QL01GABA8ESF0AITES图片预览
型号: MT250QL01GABA8ESF0AITES
PDF下载: 下载PDF文件 查看货源
内容描述: [3V, Multiple I/O, 4KB, 32KB, 64KB, Sector Erase]
分类和应用:
文件页数/大小: 97 页 / 1038 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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256Mb, 3V Multiple I/O Serial Flash Memory  
WRITE ENABLE/DISABLE Operations  
WRITE ENABLE/DISABLE Operations  
To initiate a command, S# is driven LOW and held LOW until the eighth bit of the com-  
mand code has been latched in, after which it must be driven HIGH. For extended-, du-  
al-, and quad-SPI protocols respectively, the command code is input on DQ0, DQ[1:0],  
and DQ[3:0]. If S# is not driven HIGH after the command code has been latched in, the  
command is not executed, flag status register error bits are not set, and the write enable  
latch remains cleared to its default setting of 0, providing protection against errant data  
modification.  
Table 24: WRITE ENABLE/DISABLE Operations  
Operation Name  
WRITE ENABLE (06h)  
WRITE DISABLE (04h)  
Description/Conditions  
Sets the write enable latch bit before each PROGRAM, ERASE, and WRITE command.  
Clears the write enable latch bit. In case of a protection error, WRITE DISABLE will not clear the  
bit. Instead, a CLEAR FLAG STATUS REGISTER command must be issued to clear both flags.  
Figure 31: WRITE ENABLE and WRITE DISABLE Timing  
Extended  
0
1
2
3
4
5
6
7
C
S#  
Command Bits  
LSB  
DQ0  
DQ1  
0
0
0
0
0
1
1
0
MSB  
High-Z  
Dual  
0
1
2
3
C
S#  
Command Bits  
LSB  
DQ0  
DQ1  
0
0
0
1
0
0
0
1
MSB  
Quad  
0
1
C
S#  
Command Bits  
LSB  
DQ0  
DQ1  
0
0
0
1
DQ2  
DQ3  
0
0
1
0
Don’t Care  
MSB  
1. WRITE ENABLE command sequence and code, shown here, is 06h (0000 0110 binary);  
WRITE DISABLE is identical, but its command code is 04h (0000 0100 binary).  
Note:  
CCMTD-1725822587-3368  
mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
57  
© 2014 Micron Technology, Inc. All rights reserved.  
 
 
 
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