256Mb, 3V Multiple I/O Serial Flash Memory
4-BYTE PROGRAM Operations
4-BYTE PROGRAM Operations
Table 29: 4-BYTE PROGRAM Operations
Operation Name
Description/Conditions
4-BYTE PAGE PROGRAM (12h)
4-BYTE QUAD INPUT FAST PROGRAM (34h)
PROGRAM operations can be extended to a 4-byte address range, with
[A31:0] input during address cycle.
Selection of the 3-byte or 4-byte address range can be enabled in two
ways: through the nonvolatile configuration register or through the EN-
ABLE 4-BYTE ADDRESS MODE/EXIT 4-BYTE ADDRESS MODE commands.
4-BYTE commands and DTR 4-BYTE commands function in 4-BYTE and
DTR 4-BYTE protocol regardless of settings in the nonvolatile configura-
tion register or enhanced volatile configuration register; other com-
mands function in 4-BYTE and DTR protocols only after the specific pro-
tocol is enabled by the register settings.
4-BYTE EXTENDED QUAD INPUT FAST PRO-
GRAM (3Eh)
PROGRAM Operations Timings
Figure 35: PAGE PROGRAM Command
Extended
0
7
8
C
x
C
LSB
A[MIN]
LSB
D
D
D
D
D
D
D
D
D
IN
DQ0
Command
IN
IN
IN
IN
IN
IN
IN
IN
MSB
A[MAX]
MSB
Dual
0
3
4
C
x
C
LSB
A[MIN]
LSB
D
D
D
D
D
IN
DQ[1:0]
Command
IN
IN
IN
IN
MSB
A[MAX]
MSB
Quad
0
1
2
C
x
C
LSB
A[MIN]
LSB
D
D
D
IN
DQ[3:0]
Command
IN
IN
MSB
A[MAX]
MSB
1. For extended-SPI protocol, Cx = 7 + (A[MAX] + 1); For dual-SPI protocol,
Cx = 3 + (A[MAX] + 1)/2; For quad-SPI protocol, Cx = 1 + (A[MAX] + 1)/4.
2. S# not shown. The operation is self-timed, and its duration is tPP.
Notes:
CCMTD-1725822587-3368
mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
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