256MB / 512MB (x64)
168-PIN SDRAM DIMMs
Ta b le 18: EEPROM De vice Se le ct Co d e
The most significant bit (b7) is sent first
DEVICE TYPE IDENTIFIER
CHIP ENABLE
RW
b 0
b 7
b 6
b 5
b 4
b 3
b 2
b 1
Memory Area Select Code (two arrays)
Protection Register Select Code
1
0
0
1
1
1
0
0
SA2
SA2
SA1
SA1
SA0
SA0
RW
RW
Ta b le 19: EEPROM Op e ra t in g Mo d e s
MODE
RW BIT
WC
BYTES
INITIAL SEQUENCE
V
or V
IL
1
0
1
1
0
0
1
Current Address Read
RandomAddressRead
Start, Device Select, RW = 1
IH
V
or V
IL
Start, Device Select, RW= 0, Address
RESTART, Device Select, RW= 1
Similar to Current or Random Address Read
START, Device Select, RW = 0
IH
1
V
or V
IL
IH
V
or V
IL
Oꢀ1
1
Sequential Read
Byte Write
IH
VIL
VIL
?ꢀ16
Page Write
START, Device Select, RW = 0
Ta b le 20: SERIAL Pre se n ce -De t e ct EEPROM DC Op e ra t in g Co n d it io n s
VDD = +3.3V ±0.3V; All voltages referenced to VSS
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
VDD
VIH
VIL
VOL
ILI
3
3.6
VDD + 0.5
VDD x 0.3
0.4
V
V
SUPPLY VOLTAGE
VDD x 0.7
INPUT HIGH VOLTAGE: Logic 1; All inputs
INPUT LOW VOLTAGE: Logic 0; All inputs
OUTPUT LOW VOLTAGE: IOUT = 3mA
INPUT LEAKAGE CURRENT: VIN = GND to VDD
OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD
-1
–
V
V
–
10
µA
µA
µA
ILO
–
10
ICCS
–
30
STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other
inputs = GND or 3.3V ±10%
ICC Write
ICC Read
–
–
3
1
mA
POWER SUPPLY CURRENT:
SCL Clock frequency = 100 KHz
32,64 Meg x 64 SDRAM DIMMs
SD8_16C32_64x64AG_C.fm - Rev. C 11/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
19
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