256MB / 512MB (x64)
168-PIN SDRAM DIMMs
SPD EEPROM TIMING DIAGRAM
t
t
t
F
HIGH
R
t
LOW
SCL
t
t
t
t
t
SU:STO
SU:STA
HD:STA
HD:DAT
SU:DAT
SDA IN
t
t
t
BUF
DH
AA
SDA OUT
UNDEFINED
Ta b le 21: Se ria l Pre se n ce -De t e ct EEPROM AC Op e ra t in g Co n d it io n s
VDD = +3.3V ±0.3V; All voltages referenced to VSS
PARAMETER/CONDITION
SYMBOL
MIN
0.3
MAX
3.5
–
UNITS
NOTES
tAA
tBUF
SCL LOW to SDA data-out valid
µs
µs
4.7
Time the bus must be free before a new transition can
start
tDH
tF
tHD:DAT
tHD:STA
tHIGH
tI
tLOW
tR
fSCL
tSU:DAT
tSU:STA
tSU:STO
tWRC
Data-out hold time
300
ns
ns
300
100
SDA and SCL fall time
Data-in hold time
0
4
4
µs
Start condition hold time
ClockHIGHperiod
µs
µs
ns
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
4.7
µs
1
µs
SDA and SCL rise time
SCL clock frequency
100
KHz
ns
Data-in setup time
250
4.7
4.7
µs
Start condition setup time
Stop condition setup time
WRITE cycle time
µs
10
ms
1
NOTE:
1. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of
the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.
32,64 Meg x 64 SDRAM DIMMs
SD8_16C32_64x64AG_C.fm - Rev. C 11/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
20
MICRON [ MICRON TECHNOLOGY ]
