256MB / 512MB (x64)
168-PIN SDRAM DIMMs
Ta b le 16: Ele ct rica l Ch a ra ct e rist ics a n d Re co m m e n d e d AC Op e ra t in g Co n d it io n s
Notes: 5, 6, 8, 9, 11; notes appear on page 17
Module AC timing parameters comply with PC100 and PC133 Design Specs, based on component parameters
ACCHARACTERISTICS
-13E
MAX
-133
MAX
-10E
MAX
PARAMETER
SYMBOL MIN
MIN
MIN
UNITS NOTES
tAC(3)
tAC(2)
tAH
0.8
tAS
1.5
tCH
2.5
tCL
2.5
tCK(3)
7
tCK(2)
7.5
tCKH
0.8
tCKS
1.5
tCMH
0.8
tCMS
1.5
tDH
0.8
tDS
1.5
tHZ(3)
tHZ(2)
tLZ
1
tOH
3
CL=3
CL=2
5.4
5.4
5.4
6
6
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
27
Access timefrom CLK (pos.edge)
0.8
1.5
2.5
2.5
7.5
10
1
2
Address hold time
Address setup time
CLK high-level width
CLK low-level width
Clock cycle time
3
3
CL=3
8
23
23
CL = 2
10
1
0.8
1.5
0.8
1.5
0.8
1.5
CKE hold time
CKE setup time
2
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
1
2
1
Data-in setup time
2
CL = 3
CL = 2
5.4
5.4
5.4
6
6
6
10
10
Data-out high-impedance time
Data-out low-impedance time
Data-out hold time (load)
Data-out hold time (no load)
1
3
1
3
tOHN
1.8
1.8
1.8
28
29
tRAS
37
tRC
60
tRCD
15
tREF
tRFC
66
tRP
15
tRRD
14
120,000
64
44
66
20
120,000
64
50
70
20
120,000
64
ns
ns
ns
ms
ns
ns
ns
ACTIVE to PRECHARGE command
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
Refresh period (8,192 rows)
AUTOREFRESH period
66
20
15
70
20
20
PRECHARGE command period
ACTIVE bank a to ACTIVE bank b
command
tT
tWR
0.3
1.2
0.3
1.2
0.3
1.2
ns
ns
7
Transition time
1 CLK
+
1 CLK
+
1 CLK
+
24
WRITE recovery time
7ns
14
tXSR
67
7.5ns
15
7ns
15
ns
ns
25
20
75
80
Exit SELF REFRESH to ACTIVE command
32,64 Meg x 64 SDRAM DIMMs
SD8_16C32_64x64AG_C.fm - Rev. C 11/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
15
MICRON [ MICRON TECHNOLOGY ]
