256MB, 512MB (x64, DR)
144-PIN SDRAM SODIMM
Table 20: Serial Presence-Detect Matrix
“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; VDD = +3.3V 0.3V
BYTE
DESCRIPTION
ENTRY (VERSION) MT16LSDF3264H
MT16LSDF6464H
0
1
2
3
4
5
6
7
8
9
128
256
80
08
04
0C
0A
02
40
00
01
80
08
04
0D
0A
02
40
00
01
Number of bytes used by Micron
Total number of SPD memory bytes
Memory type
SDRAM
12 or 13
10
Number of row addresses
Number of column addresses
Number of banks
2
64
Module data width
0
Module data width (continued)
Module voltage interface levels
SDRAM cycle time, tCK
(CL = 3)
LVTTL
7ns (-13E)
7.5ns (-133)
8ns (-10E)
70
75
80
70
75
80
SDRAM access from clock, tAC
(CL = 3)
10
5.4ns (-13E/-133)
6ns (-10E)
54
60
54
60
11
12
NONE
00
80
00
82
Module configuration type
Refresh rate/type
15.6µs
or 7.81µs/self
13
14
15
8
08
00
01
08
00
01
SDRAM width (primary SDRAM)
Error-checking SDRAM data width
MIN clock delay from back-to-back random
column addresses, tCCD
1
16
17
18
19
20
21
22
23
1, 2, 4, 8, page
8F
04
06
01
01
00
0E
8F
4
Burst lengths supported
4
Number of banks on SDRAM device
CAS latencies supported
2, 3
6
0
01
01
00
0E
CS latency
0
Unbuffered
14
WE latency
SDRAM module attributes
SDRAM device attributes: General
SDRAM cycle time, tCK
(CL = 2)
7.5ns (13E)
10ns (-133/-10E)
75
A0
75
A0
SDRAM access from CLK, tAC
(CL = 2)
SDRAM cycle time, tCK
(CL = 1)
SDRAM access from CLK, tAC
(CL = 1)
24
25
26
5.4ns (-13E)
6ns (-133/-10E)
54
60
54
60
–
–
00
00
00
00
MIN row precharge time, tRP
27
28
15ns (-13E)
20ns (-133/-10E)
0F
14
0F
14
MIN row active-to-row active, tRRD
14ns (-13E)
15ns (-133)
20ns (-10E)
0E
0F
14
0E
0F
14
MIN RAS#-to-CAS# delay, tRCD
MIN RAS# pulse width, tRAS
29
30
15ns (-13E)
20ns (-133/-10E)
0F
14
0F
14
45ns (-13E)
44ns (133)
50ns (-10E)
2D
2C
32
2D
2C
32
pdf: 09005aef807924d2, source: 09005aef807924f1
SDF16C32_64x64HG.fm - Rev. E 4/06 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
20
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