256MB, 512MB (x64, DR)
144-PIN SDRAM SODIMM
Table 16: EEPROM Device Select Code
Most significant bit (b7) is sent first
DEVICE TYPE IDENTIFIER
CHIP ENABLE
b2
RW
b0
b7
b6
b5
b4
b3
b1
1
0
0
1
1
1
0
0
SA2
SA2
SA1
SA1
SA0
SA0
RW
RW
Memory area select code (two arrays)
Protection register select code
Table 17: EEPROM Operating Modes
MODE
RW# BIT
WC
BYTES
INITIAL SEQUENCE
1
0
1
1
0
0
VIH or VIL
VIH or VIL
VIH or VIL
VIH or VIL
VIL
1
1
Current address READ
Random address READ
START, device select, RW = 1
START, device select, RW = 0, Address
RESTART, device select, RW = 1
≥1
1
Sequential READ
Byte WRITE
similar to current or random address READ
START, device select, RW = 0
VIL
≤16
Page WRITE
START, device select, RW# = 0
Figure 9: SPD EEPROM Timing Diagram
t
t
t
F
HIGH
R
t
LOW
SCL
t
t
t
t
t
SU:STA
HD:STA
HD:DAT
SU:DAT
SU:STO
SDA In
t
t
t
DH
AA
BUF
SDA Out
UNDEFINED
pdf: 09005aef807924d2, source: 09005aef807924f1
SDF16C32_64x64HG.fm - Rev. E 4/06 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
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