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MT16LSDF3264LHG-133 参数 Datasheet PDF下载

MT16LSDF3264LHG-133图片预览
型号: MT16LSDF3264LHG-133
PDF下载: 下载PDF文件 查看货源
内容描述: [SMALL-OUTLINE SDRAM MODULE]
分类和应用: 时钟动态存储器光电二极管内存集成电路
文件页数/大小: 22 页 / 476 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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256MB, 512MB (x64, DR)  
144-PIN SDRAM SODIMM  
SPD Clock and Data Conventions  
Data states on the SDA line can change only during  
SCL LOW. SDA state changes during SCL HIGH are  
reserved for indicating start and stop conditions (see  
Figures 6, and 7).  
SPD Acknowledge  
Acknowledge is a software convention used to indi-  
cate successful data transfers. The transmitting device,  
either master or slave, will release the bus after trans-  
mitting eight bits. During the ninth clock cycle, the  
receiver will pull the SDA line LOW to acknowledge  
that it received the eight bits of data (see Figure 8).  
The SPD device will always respond with an  
acknowledge after recognition of a start condition and  
its slave address. If both the device and a WRITE oper-  
ation have been selected, the SPD device will respond  
with an acknowledge after the receipt of each subse-  
quent eight bit word. In the read mode the SPD device  
will transmit eight bits of data, release the SDA line and  
monitor the line for an acknowledge. If an acknowl-  
edge is detected and no stop condition is generated by  
the master, the slave will continue to transmit data. If  
an acknowledge is not detected, the slave will termi-  
nate further data transmissions and await the stop  
condition to return to standby power mode.  
SPD Start Condition  
All commands are preceded by the start condition,  
which is a HIGH-to-LOW transition of SDA when SCL  
is HIGH. The SPD device continuously monitors the  
SDA and SCL lines for the start condition and will not  
respond to any command until this condition has been  
met.  
SPD Stop Condition  
All communications are terminated by a stop condi-  
tion, which is a LOW-to-HIGH transition of SDA when  
SCL is HIGH. The stop condition is also used to place  
the SPD device into standby power mode.  
Figure 6: Data Validity  
Figure 7: Definition of Start and Stop  
SCL  
SCL  
SDA  
SDA  
Start  
bit  
Stop  
bit  
Data stable  
Data change  
Data stable  
Figure 8: Acknowledge Response From Receiver  
((  
))  
SCL from master  
((  
))  
Data output  
from transmitter  
((  
))  
((  
))  
Data output  
from receiver  
Acknowledge  
pdf: 09005aef807924d2, source: 09005aef807924f1  
SDF16C32_64x64HG.fm - Rev. E 4/06 EN  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2006 Micron Technology, Inc. All rights reserved.  
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