256MB, 512MB (x64, DR)
144-PIN SDRAM SODIMM
Notes
t
1. All voltages referenced to VSS.
2. This parameter is sampled. VDD, VDDQ = +3.3V; f =
16. Timing actually specified by WR.
17. Required clocks are specified by JEDEC function-
ality and are not dependent on any timing param-
eter.
18. The IDD current will increase or decrease propor-
tionally according to the amount of frequency
alteration for the test condition.
19. Address transitions average one transition every
two clocks.
20. CLK must be toggled a minimum of two times
during this period.
1 MHz, T = 25°C; pin under test biased at 1.4V.
A
3. IDD is dependent on output loading and cycle
rates. Specified values are obtained with mini-
mum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
indicate cycle time at which proper operation
over the full temperature range is ensured (0°C ≤
T
≤ +70°C).
A
t
t
6. An initial pause of 100µs is required after power-
up, followed by two AUTO REFRESH commands,
before proper device operation is ensured. (VDD
and VDDQ must be powered up simultaneously.
VSS and VSSQ must be at same potential.) The two
AUTO REFRESH-command wake-ups should be
21. Based on CK = 10ns for -10E, and CK = 7.5ns for -
133 and -13E.
22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse
width ≤ 3ns, and the pulse width cannot be greater
than one third of the cycle rate. VIL undershoot:
VIL (MIN) = -2V for a pulse width ≤ 3ns.
23. The clock frequency must remain constant (stable
clock is defined as a signal cycling within timing
constraints specified for the clock pin) during
access or precharge states (READ, WRITE, includ-
t
repeated any time the REF refresh requirement is
exceeded.
t
7. AC characteristics assume T = 1ns.
8. In addition to meeting the transition rate specifi-
cation, the clock and CKE must transit between
VIH and VIL (or between VIL and VIH) in a mono-
tonic manner.
t
ing WR, and PRECHARGE commands). CKE may
be used to reduce the data rate.
24. Auto precharge mode only. The precharge time
t
9. Outputs measured at 1.5V with equivalent load:
( RP) begins at 7ns for -13E; 7.5ns for -133 and 7ns
for -10E after the first clock delay, after the last
WRITE is executed. May not exceed limit set for
precharge mode.
Q
50pF
25. Precharge mode only.
t
26. JEDEC and PC100 specify three clocks.
10. HZ defines the time at which the output achieves
t
the open circuit condition; it is not a reference to
VOH or VOL. The last valid data element will meet
27. AC for -133/-13E at CL = 3 with no load is 4.6ns
and is guaranteed by design.
28. Parameter guaranteed by design.
t
OH before going High-Z.
t
11. AC timing and IDD tests have VIL = 0V and VIH = 3V,
with timing referenced to 1.5V crossover point. If
the input transition time is longer than 1ns, then
the timing is referenced at VIL (MAX) and VIH
(MIN) and no longer at the 1.5V crossover point.
12. Other input signals can change no more than
once every two clocks and are otherwise at valid
VIH or VIL levels.
29. For -10E, CL = 2 and CK = 10ns; for -133, CL = 3
t
t
and CK = 7.5ns; for -13E, CL = 2 and CK = 7.5ns.
30. CKE is HIGH during refresh command period
t
RFC (MIN), else CKE is LOW. The IDD6 limit is
actually a nominal value and does not result in a
fail value.
31. Refer to device data sheet for timing waveforms.
t
32. The value of RAS used in -13E speed grade mod-
13. IDD specifications are tested after the device is
properly initialized.
t
t
ule SPDs is calculated from RC - RP = 45ns.
33. Leakage number reflects the worst case leakage
possible through the module pin, not what each
memory device contributes.
t
14. Timing actually specified by CKS; clock(s) speci-
fied as a reference only at minimum cycle rate.
t
t
15. Timing actually specified by WR plus RP; clock(s)
specified as a reference only at minimum cycle
rate.
pdf: 09005aef807924d2, source: 09005aef807924f1
SDF16C32_64x64HG.fm - Rev. E 4/06 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
16
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