256Mb: 3V Embedded Parallel NOR Flash
Erase Operations
Erase Operations
CHIP ERASE Command
The CHIP ERASE (80/10h) command erases the entire chip. Six bus WRITE operations
are required to issue the command and start the program/erase controller.
Protected blocks are not erased. If all blocks are protected, the CHIP ERASE operation
appears to start, but will terminate within approximately100μs, leaving the data un-
changed. No error is reported when protected blocks are not erased.
During the CHIP ERASE operation, the device ignores all other commands, including
ERASE SUSPEND. It is not possible to abort the operation. All bus READ operations dur-
ing CHIP ERASE output the status register on the data I/Os. See the Status Register sec-
tion for more details.
After the CHIP ERASE operation completes, the device returns to read mode, unless an
error has occurred. If an error occurs, the device will continue to output the status regis-
ter. A READ/RESET command must be issued to reset the error condition and return to
read mode.
The CHIP ERASE command sets all of the bits in unprotected blocks of the device to 1.
All previous data is lost.
The operation is aborted by performing a reset or by powering-down the device. In this
case, data integrity cannot be ensured, and it is recommended that the entire chip be
erased again.
UNLOCK BYPASS CHIP ERASE Command
When the device is in unlock bypass mode, the UNLOCK BYPASS CHIP ERASE (80/10h)
command can be used to erase all memory blocks at one time. The command requires
only two bus WRITE operations instead of six using the standard CHIP ERASE com-
mand. The final bus WRITE operation starts the program/erase controller.
The UNLOCK BYPASS CHIP ERASE command behaves the same way as the CHIP
ERASE command: the operation cannot be aborted, and a bus READ operation to the
memory outputs the status register.
BLOCK ERASE Command
The BLOCK ERASE (80/30h) command erases a list of one or more blocks. It sets all of
the bits in the unprotected selected blocks to 1. All previous data in the selected blocks
is lost.
Six bus WRITE operations are required to select the first block in the list. Each addition-
al block in the list can be selected by repeating the sixth bus WRITE operation using the
address of the additional block. After the command sequence is written, a block erase
timeout occurs. During the timeout period, additional block addresses and BLOCK
ERASE commands can be written. After the program/erase controller has started, it is
not possible to select any more blocks. Therefore, each additional block must be selec-
ted within the timeout period of the last block. The timeout timer restarts when an ad-
ditional block is selected. After the sixth bus WRITE operation, a bus READ operation
outputs the status register. Bus READ operations from banks different from those that
include the blocks being erased output the memory array content. See the WE#-Con-
PDF: 09005aef84ecabef
m29dw_256g.pdf - Rev. A 10/12 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
42
© 2012 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
