256Mb: 3V Embedded Parallel NOR Flash
Erase Operations
trolled Program waveforms for details on how to identify if the program/erase controller
has started the BLOCK ERASE operation.
After the BLOCK ERASE operation completes, the device returns to read mode, unless
an error has occurred. If an error occurs, bus READ operations will continue to output
the status register. A READ/RESET command must be issued to reset the error condi-
tion and return to read mode.
If any selected blocks are protected, they are ignored, and all the other selected blocks
are erased. If all of the selected blocks are protected, the BLOCK ERASE operation ap-
pears to start, but will terminate within approximately100μs, leaving the data un-
changed. No error condition is given when protected blocks are not erased.
During the BLOCK ERASE operation, the device ignores all commands except the
ERASE SUSPEND command and the READ/RESET command, which is accepted only
during the timeout period. The operation is aborted by performing a reset or powering-
down the device. In this case, data integrity cannot be ensured, and it is recommended
that the aborted blocks be erased again.
UNLOCK BYPASS BLOCK ERASE Command
When the device is in unlock bypass mode, the UNLOCK BYPASS BLOCK ERASE
(80/30h) command can be used to erase one or more memory blocks at a time. The
command requires two bus WRITE operations instead of six using the standard BLOCK
ERASE command. The final bus WRITE operation latches the address of the block and
starts the program/erase controller.
To erase multiple blocks (after the first two bus WRITE operations have selected the first
block in the list), each additional block in the list can be selected by repeating the sec-
ond bus WRITE operation using the address of the additional block.
The UNLOCK BYPASS BLOCK ERASE command behaves the same way as the BLOCK
ERASE command: the operation cannot be aborted, and a bus READ operation to the
memory outputs the status register. Bus READ operations from banks different from
those that include the blocks being erased output the memory array content. See the
BLOCK ERASE Command section for details.
ERASE SUSPEND Command
The ERASE SUSPEND (B0h) command temporarily suspends a BLOCK ERASE opera-
tion. One bus WRITE operation with the block address is required to issue the com-
mand.
After the command sequence is written, a minimum block erase timeout occurs. During
the timeout period, additional block addresses and block erase commands can be writ-
ten.
The program/erase controller suspends the ERASE operation within the erase suspend
latency time of the ERASE SUSPEND command being issued. However, when the
ERASE SUSPEND command is written during the block erase timeout, the device im-
mediately terminates the timeout period and suspends the ERASE operation. After the
program/erase controller has stopped, the device operates in read mode, and the erase
is suspended.
During an ERASE SUSPEND operation, it is possible to read and execute PROGRAM op-
erations or WRITE TO BUFFER PROGRAM operations in blocks that are not suspended.
PDF: 09005aef84ecabef
m29dw_256g.pdf - Rev. A 10/12 EN
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