256Mb: 3V Embedded Parallel NOR Flash
Program Operations
WRITE TO BUFFER PROGRAM RESUME Command
The WRITE TO BUFFER PROGRAM RESUME (30h) command must be issued to exit a
write to buffer program suspend mode and resume a WRITE TO BUFFER PROGRAM
operation. The controller can use DQ7 or DQ6 status bits to determine the status of the
WRITE TO BUFFER PROGRAM operation. After a WRITE TO BUFFER PROGRAM RE-
SUME command is issued, subsequent WRITE TO BUFFER PROGRAM RESUME com-
mands are ignored. Another WRITE TO BUFFER PROGRAM SUSPEND command can
be issued after the device has resumed programming.
ENTER ENHANCED BUFFERED Command
The ENTER ENHANCED BUFFERED command is used to allow execution of the en-
hanced buffered program commands. The device accepts only these following com-
mands after the ENTER ENHANCED BUFFERED command is issued; any other com-
mand is ignored:
• ENHANCED BUFFERED PROGRAM (can be issued multiple times once the ENTER
ENHANCED BUFFERED command is executed)
• ENHANCED BUFFERED PROGRAM ABORT/RESET
• EXIT ENHANCED BUFFERED PROGRAM
To ensure the ENTER ENHANCED BUFFERED command has completed successfully
and the device is ready to receive one of the commands listed above, it is recommended
to monitor toggle bit (DQ6).
ENHANCED BUFFERED PROGRAM Command
The ENHANCED BUFFERED PROGRAM command makes use of a 256-word write buf-
fer to speed up programming. Each write buffer has the same A23-A8 addresses. This
command dramatically reduces system programming time compared to both the
standard non-buffered PROGRAM command and the WRITE TO BUFFER command.
When issuing the ENHANCED BUFFERED PROGRAM command, the VPP/WP pin can
be held HIGH or raised to VPPH (see Program/Erase Characteristics). The following suc-
cessive steps are required to issue the ENHANCED BUFFERED PROGRAM command:
First, the ENTER ENHANCED BUFFERED PROGRAM command issued. Next, one bus
WRITE cycle sets up the ENHANCED BUFFERED PROGRAM command. The set-up
code can be addressed to any location within the targeted block. Then, a second bus
WRITE cycle loads the first address and data to be programmed. There are a total of 256
address and data loading cycles. When the 256 words are loaded to the buffer, a third
WRITE cycle programs the content of the buffer. Last, when the command completes,
the EXIT ENHANCED BUFFERED PROGRAM command is issued.
Address/data cycles must be loaded in an increasing address order, from A[7:0] =
00000000 to A[7:0] = 11111111 until all 256 words are loaded. Invalid address combina-
tions or the incorrect sequence of bus WRITE cycles will abort the ENHANCED BUF-
FERED PROGRAM command.
The status register bits DQ1, DQ5, DQ6, DQ7 can be used to monitor the device status
during an ENHANCED BUFFERED PROGRAM operation.
An external 12V supply can be used to improve programming efficiency.
PDF: 09005aef84ecabef
m29dw_256g.pdf - Rev. A 10/12 EN
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