P33-65nm
Table 7:
Command Bus Cycles (Sheet 1 of 2)
First Bus Cycle
Second Bus Cycle
(1)
Bus
Cycles
Mode
Command
(1)
(2)
(2)
Oper
Addr
Data
Oper
Addr
Data
Read Array
1
Write
DnA
DnA
0xFF
-
-
-
Read Device
Identifier
≥ 2
Write
0x90
Read
DBA + IA
ID
Read
Read CFI
≥ 2
2
Write
Write
Write
Write
Write
DnA
DnA
DnA
WA
0x98
0x70
0x50
0x40
0xE8
Read
Read
-
DBA + CFI-A
CFI-D
SRD
-
Read Status Register
Clear Status Register
Word Program
DnA
-
1
2
Write
Write
WA
WA
WD
(3)
Buffered Program
> 2
WA
N - 1
Program
Buffered Enhanced
Factory Program
(BEFP)
> 2
Write
WA
0x80
Write
WA
0xD0
(4)
Erase
Block Erase
2
1
Write
Write
BA
0x20
0xB0
Write
-
BA
-
0xD0
-
Program/Erase
Suspend
DnA
Suspend
Program/Erase
Resume
1
Write
DnA
0xD0
-
-
-
Lock Block
2
2
2
2
Write
Write
Write
Write
BA
BA
0x60
0x60
0x60
0xC0
Write
Write
Write
Write
BA
BA
0x01
0xD0
0x2F
Unlock Block
Lock-down Block
Program OTP register
BA
BA
Protection
PRA
OTP-RA
OTP-D
Program Lock
Register
2
2
Write
Write
LRA
0xC0
0x60
Write
Write
LRA
LRD
Program Read
Configuration Configuration
RCD
RCD
0x03
Register
Datasheet
19
Aug 2009
OrderNumber:320003-08
MICRON [ MICRON TECHNOLOGY ]
