P33-65nm
3.0
Ballouts
Figure 4: 56-Lead TSOP Pinout (256-Mbit)
WAIT
A17
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
A16
A15
2
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
ADV#
CLK
3
A14
A13
A12
A11
A10
A9
4
5
6
7
8
9
A23
A22
A21
VSS
VCC
WE#
WP#
A20
A19
A18
A8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Numonyx™
StrataFlash® Embedded Memory (P33)
RST#
VPP
DQ11
DQ3
DQ10
DQ2
VCCQ
DQ9
DQ1
DQ8
DQ0
VCC
OE#
56-Lead TSOP Pinout
14 mm x 20 mm
Top View
A7
A6
A5
A4
A3
A2
VSS
CE#
A24
RFU
VSS
A1
Notes:
1.
2.
3.
4.
A1 is the least significant address bit.
A24 is valid for 256-Mbit densities; otherwise, it is a no connect (NC).
No Internal Connection on VCC Pin 13; it may be driven or floated. For legacy designs, pin can be tied to Vcc.
One dimple on package denotes Pin 1, which will always be in the upper left corner of the package, in reference to the
product mark.
Datasheet
11
Aug 2009
OrderNumber:320003-08
MICRON [ MICRON TECHNOLOGY ]
