256Mb and 512Mb (256Mb/256Mb), P30-65nm
AC Write Specifications
9. When doing a READ STATUS operation following any command that alters the status
register, tWHGL is 20ns.
10. Add 10ns if the WRITE operation results in an RCR or block lock status change, for the
subsequent READ operation to reflect this change.
11. These specs are required only when the device is in a synchronous mode and the clock is
active during an address setup phase.
12. This specification must be complied with customer’s writing timing. The result would be
unpredictable if there is any violation to this timing specification.
PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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