256Mb and 512Mb (256Mb/256Mb), P30-65nm
Signal Descriptions
Table 7: TSOP and Easy BGA Signal Descriptions (Continued)
Symbol
Type
Name and Function
WAIT
Output
Wait: Indicates data valid in synchronous array or non-array burst reads. Read configura-
tion register bit 10 (RCR.10, WT) determines its polarity when asserted. This signal's active
output is VOL or VOH when CE# and OE# are VIL. WAIT is High-Z if CE# or OE# is VIH.
• In synchronous array or non-array read modes, this signal indicates invalid data when as-
serted and valid data when de-asserted.
• In asynchronous page mode, and all write modes, this signal is de-asserted.
VCC
Power
Device core power supply: Core (logic) source voltage. Writes to the array are inhibited
when VCC ≤ VLKO. Operations at invalid VCC voltages should not be attempted.
VCCQ
VSS
Power
Power
—
Output power supply: Output-driver source voltage.
Ground: Connect to system ground. Do not float any VSS connection.
RFU
Reserved for future use: Reserved by Micron for future device functionality and en-
hancement. These should be treated in the same way as a DU signal.
DU
NC
—
—
Do not use: Do not connect to any other signal, or power supply; must be left floating.
No connect: No internal connection; can be driven or floated.
Table 8: QUAD+ SCSP Signal Descriptions
Symbol
Type
Name and Function
A[MAX:0]
Input
Address inputs: Device address inputs. 256Mb: A[23:0]; 512Mb: A[24:0]. Note: The virtual
selection of the 256Mb top parameter die in the dual-die 512Mb configuration is accom-
plished by setting A24 HIGH.
Note: The address pins unused in design should not be left floating; tie them to VCCQ or
VSS according to specific design requirements. Note: When handling the QUAD + SCSP
package, note that LSB is A0; address conversion is necessary.
ADV#
Input
Input
Address valid: Active LOW input. During synchronous READ operations, addresses are
latched on the rising edge of ADV#, or on the next valid CLK edge with ADV# LOW, which-
ever occurs first.
In asynchronous mode, the address is latched when ADV# goes HIGH or continuously flows
through if ADV# is held LOW.
Note: Designs not using ADV# must tie it to VSS to allow addresses to flow through.
F1-CE#
Flash chip enable: Active LOW input. F1-CE# LOW selects the associated die. When asser-
ted, internal control logic, input buffers, decoders, and sense amplifiers are active. When
de-asserted, the associated die is deselected, power is reduced to standby levels, data and
wait outputs are placed in High-Z.
Note: F1-CE# must be driven HIGH when device is not in use.
CLK
Input
Input
Clock: Synchronizes the device with the system bus frequency in synchronous-read mode.
During synchronous READ operations, addresses are latched on the rising edge of ADV#,
or on the next valid CLK edge with ADV# LOW, whichever occurs first.
Note: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS.
F1-OE#
Output enable: Active LOW input. F1-OE# LOW enables the device’s output data buffers
during READ cycles. F1-OE# HIGH places the data outputs and wait in High-Z.
PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN
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