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JS28F256P30B 参数 Datasheet PDF下载

JS28F256P30B图片预览
型号: JS28F256P30B
PDF下载: 下载PDF文件 查看货源
内容描述: 美光并行NOR闪存的嵌入式存储器( P30-65nm ) [Micron Parallel NOR Flash Embedded Memory (P30-65nm)]
分类和应用: 闪存存储
文件页数/大小: 98 页 / 1366 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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256Mb and 512Mb (256Mb/256Mb), P30-65nm  
Device Command Codes  
Device Command Codes  
The system CPU provides control of all in-system READ, WRITE, and ERASE operations  
of the device via the system bus. The device manages all block-erase and word-program  
algorithms.  
Device commands are written to the CUI to control all device operations. The CUI does  
not occupy an addressable memory location; it is the mechanism through which the  
device is controlled.  
Note: For a dual device, all setup commands should be re-issued to the device when a  
different die is selected.  
Table 10: Command Codes and Definitions  
Mode  
Device Mode  
Read array  
Code  
0xFF  
Description  
Read  
Places the device in read array mode. Array data is output on DQ[15:0].  
Read status register  
0x70  
Places the device in read status register mode. The device enters this  
mode after a PROGRAM or ERASE command is issued. Status register  
data is output on DQ[7:0].  
Read device ID or  
read configuration  
register  
0x90  
Places device in read device identifier mode. Subsequent reads output  
manufacturer/device codes, configuration register data, block lock sta-  
tus, or protection register data on DQ[15:0].  
Read CFI  
0x98  
0x50  
0x40  
Places the device in read CFI mode. Subsequent reads output CFI infor-  
mation on DQ[7:0].  
Clear status register  
Word program setup  
The device sets status register error bits. The clear status register com-  
mand is used to clear the SR error bits.  
Write  
First cycle of a 2-cycle programming command; prepares the CUI for a  
WRITE operation. On the next write cycle, the address and data are  
latched and the device executes the programming algorithm at the ad-  
dressed location. During PROGRAM operations, the device responds  
only to READ STATUS REGISTER and PROGRAM SUSPEND commands.  
CE# or OE# must be toggled to update the status register in asynchro-  
nous read. CE# or ADV# must be toggled to update the status register  
data for synchronous non-array reads. The READ ARRAY command  
must be issued to read array data after programming has finished.  
Buffered program  
0xE8  
0xD0  
This command loads a variable number of words up to the buffer size  
of 512 words onto the program buffer.  
Buffered program  
confirm  
The CONFIRM command is issued after the data streaming for writing  
into the buffer is completed. The device then performs the buffered  
program algorithm, writing the data from the buffer to the memory  
array.  
BEFP setup  
0x80  
0xD0  
First cycle of a two-cycle command; initiates buffered enhanced factory  
program mode (BEFP). The CUI then waits for the BEFP CONFIRM com-  
mand, 0xD0, that initiates the BEFP algorithm. All other commands are  
ignored when BEFP mode begins.  
BEFP confirm  
If the previous command was BEFP SETUP (0x80), the CUI latches the  
address and data, and prepares the device for BEFP mode.  
PDF: 09005aef84566799  
p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
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© 2013 Micron Technology, Inc. All rights reserved.