P30-65nm SBC
Table 8:
Device Identifier Information (Sheet 2 of 2)
(1,2)
Item
Address
Data(x16)
Lock Register 1
0x89
PR-LK1 OTP Register lock data
User OTP Register data
128-bit User-Programmable OTP Registers
0x8A–0x109
Notes:
1.
2.
3.
BBA = Block Base Address.
DBA = Device base Address, Numonyx reserves other configuration address locations.
The GPR is used as read out register for Extended Function interface command.
Table 9:
Device ID codes
ID Code Type
Device Density
Device Identifier Codes
64-Mbit
128-Mbit
64-Mbit
8817
8818
881A
881B
Top Boot
Bottom Boot
128-Mbit
7.3
7.4
Read CFI
The Read CFI command instructs the device to output Common Flash Interface data
when read. See Figure 6.1, “Device Command Codes” on page 19. Section A.1,
“Common Flash Interface” on page 61 shows CFI information and address offsets
within the CFI database.
Read Status Register
To read the Status Register, issue the Read Status Register command at any address.
Status Register information is available to which the Read Status Register, Word
Program, or Block Erase command was issued. SRD is automatically made available
following a Word Program, Block Erase, or Block Lock command sequence. Reads from
the device after any of these command sequences outputs the device’s status until
another valid command is written (e.g. the Read Array command).
The Status Register is read using single asynchronous-mode or synchronous burst
mode reads. SRD is output on DQ[7:0], while 0x00 is output on DQ[15:8]. In
asynchronous mode the falling edge of OE#, or CE# (whichever occurs first) updates
and latches the Status Register contents. However, when reading the Status Register in
synchronous burst mode, CE# or ADV# must be toggled to update SRD.
The Device Ready Status bit (SR.7) provides overall status of the device. SR[6:1]
present status and error information about the program, erase, suspend, VPP, and
block-locked operations.
See Table 12, “Status Register Description” on page 34 for the description of the Status
Register.
7.5
Clear Status Register
The Clear Status Register command clears the Status Register. It functions independent
of VPP. The WSM sets and clears SR.7, but it sets bits SR[5:3,1] without clearing them.
The Status Register should be cleared before starting a command sequence to avoid
any ambiguity. A device reset also clears the Status Register.
Datasheet
23
Apr 2010
OrderNumber:208033-02
MICRON [ MICRON TECHNOLOGY ]
