PIC32
• Updated Section 12.2 “With the PE”
Revision J (August 2011) (Continued)
• Updated Step 3 in Initiate Flash Row Write Op
Codes (see Table 13-1)
• Updated the PGCx signal in Entering Enhanced
ICSP Mode (see Figure 7-1)
• Updated Step 1 in Verify Device Op Codes (see
Table 14-1)
• Updated the Erase Device block diagram (see
Figure 9-1)
• Updated the interval in Section 15.1 “4-wire
Interface” and Section 15.2 “2-wire Interface”
• Added a new step 4 to the process to erase a target
device in Section 9.0 “Erasing the Device”
• Added a note regarding the PE location in
Section 16.0 “The Programming Executive”
• Updated the MCLR signal in 2-Wire Exit Test
Mode (see Figure 15-2)
• Added references to the Operand field throughout
Section 16.2 “The PE Command Set”
• Updated the PE Command Set with the following
commands and modified Note 2 (see Table 16-2):
• Updated the PROGRAMCommand Algorithm (see
Figure 16-9)
- PROGRAM_CLUSTER
- GET_DEVICEID
- CHANGE_CFG
• Updated the mask values for All PIC32MX1XX
and PIC32MX2XX devices, and DEVCFG3 for all
devices (see Table 17-1)
• Added a second note to Section 16.2.11
“GET_CRC Command”
• Updated the DCR value (see Section 17.4.3
“Calculating for “DCR” in the Checksum
Formula” and Table 17-2)
• Updated the Address and Length descriptions in the
PROGRAM_CLUSTERFormat (see Table 16-13)
• Added a note after the CHANGE_CFGResponse (see
Figure 16-27)
• Updated the Checksum Calculation Process (see
Example 17-1)
• Updated the DEVCFG0 and DEVCFG1 values for
All PIC32MX1XX and All PIC32MX2XX devices in
Table 17-1
• Added these new devices to the Code Memory Size
table (see Table 5-1) and the Device IDs and
Revision table (see Table 18-4):
• The following changes were made to the AC/DC
Characteristics and Timing Requirements
(Table 20-1):
- PIC32MX420F032H
- PIC32MX330F064H
- PIC32MX330F064L
- PIC32MX430F064H
- PIC32MX430F064L
- PIC32MX340F128H
- PIC32MX340F128L
- PIC32MX350F128H
- PIC32MX350F128L
- PIC32MX350F256H
- PIC32MX350F256L
- PIC32MX440F128H
- PIC32MX440F128L
- PIC32MX450F128H
- PIC32MX450F128L
- PIC32MX440F256H
- PIC32MX450F256H
- PIC32MX450F256L
- PIC32MX460F256L
- PIC32MX340F512H
- PIC32MX360F512H
- PIC32MX370F512H
- PIC32MX370F512L
- PIC32MX440F512H
- PIC32MX460F512L
- PIC32MX470F512H
- PIC32MX470F512L
- Updated the Min. value for parameter D111 (VDD)
- Added parameter D114 (IPEAK)
- Removed parameters P2, P3, P4, P4A, P5, P8
and P10
• Removed Appendix C: “Flash Program Memory
Data Sheet Clarification”
• Minor updates to text and formatting were
incorporated throughout the document
Revision K (July 2012)
This revision includes the following updates:
• All occurrences of PGC and PGD were changed to:
PGEC and PGED, respectively
• Added a Note to Section 18.2 “Device Code
Protection bit (CP)”
• Updated Section 1.0 “Device Overview” with a list
of all major topics in this document
• Added the EJTAG Control Register (see
Register 19-1)
• Added Section 2.3 “Data Sizes”
• Updated Section 19.2.4 “ETAP_EJTAGBOOT
Command”
• Updated Section 4.0 “Connecting to the Device”
• Added Note 2 to Connections for the On-chip
Regulator (see Figure 4-2)
• AC/DC Characteristics and Timing Requirements
updates (see Table 20-1):
• Added Note 2 to the 4-wire and 2-wire Interface Pins
tables (see Table 4-1 and Table 4-2)
- Removed parameter D112
- Replaced Notes 1 and 2 with a new Note 1
• Updated Section 7.0 “Entering 2-Wire Enhanced
ICSP Mode”
- Updated parameters D111, D113, D114, D031,
D041, D080, D090, D012, D013, P11, P12, and
P13
• Updated Entering Serial Execution Mode (see
Figure 10-1)
• Minor updates to text and formatting were
incorporated through the document
• Updated step 11 in Section 10.2 “2-wire Interface”
DS61145L-page 64
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