PIC24FJ64GA104 FAMILY
REGISTER 7-32: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER
R-0
U-0
—
R/W-0
U-0
—
R-0
R-0
R-0
R-0
CPUIRQ
VHOLD
ILR3
ILR2
ILR1
ILR0
bit 15
bit 8
U-0
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
VECNUM6
VECNUM5
VECNUM4
VECNUM3
VECNUM2
VECNUM1
VECNUM0
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
CPUIRQ: Interrupt Request from Interrupt Controller CPU bit
1= An interrupt request has occurred but has not yet been Acknowledged by the CPU; this happens
when the CPU priority is higher than the interrupt priority
0= No interrupt request is unacknowledged
bit 14
bit 13
Unimplemented: Read as ‘0’
VHOLD: Vector Number Capture Configuration bit
1= The VECNUM bits contain the value of the highest priority pending interrupt
0= The VECNUM bits contain the value of the last Acknowledged interrupt (i.e., the last interrupt that
has occurred with higher priority than the CPU, even if other interrupts are pending)
bit 12
Unimplemented: Read as ‘0’
bit 11-8
ILR<3:0>: New CPU Interrupt Priority Level bits
1111= CPU Interrupt Priority Level is 15
•
•
•
0001= CPU Interrupt Priority Level is 1
0000= CPU Interrupt Priority Level is 0
bit 7
Unimplemented: Read as ‘0’
bit 6-0
VECNUM<6:0>: Pending Interrupt Vector ID bits (pending vector number is VECNUM + 8)
0111111= Interrupt Vector pending is number 135
•
•
•
0000001= Interrupt Vector pending is number 9
0000000= Interrupt Vector pending is number 8
DS39951C-page 98
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
