PIC24FJ64GA104 FAMILY
REGISTER 7-27: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
R/W-0
MI2C2IP2
MI2C2IP1
MI2C2IP0
bit 15
bit 8
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
SI2C2IP2
SI2C2IP1
SI2C2IP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-11
bit 10-8
Unimplemented: Read as ‘0’
MI2C2IP<2:0>: Master I2C2 Event Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SI2C2IP<2:0>: Slave I2C2 Event Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
DS39951C-page 94
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
