PIC24FJ32GA104T-I/PT 参数 Datasheet PDF下载

型号：	PIC24FJ32GA104T-I/PT
PDF下载：	下载PDF文件查看货源
内容描述：	44分之28引脚， 16位通用闪存微控制器采用nanoWatt XLP技术 [28/44-Pin, 16-Bit General Purpose Flash Microcontrollers with nanoWatt XLP Technology]
分类和应用：	闪存微控制器
文件页数/大小：	308 页 / 2416 K
品牌：	MICROCHIP [ MICROCHIP ]

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TABLE 4-9:

I²C™ REGISTER MAP

All

Resets

File Name

Addr

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

I2C1RCV

I2C1TRN

I2C1BRG

I2C1CON

0200

0202

0204

0206

—

Receive Register

Transmit Register

0000

00FF

0000

1000

—

Baud Rate Generator Register

I2CEN

I2CSIDL SCLREL IPMIEN

A10M

DISSLW

SMEN

GCEN

STREN

I2COV

ACKDT ACKEN

D/A

RCEN

PEN

R/W

RSEN

RBF

SEN

TBF

I2C1STAT

I2C1ADD

I2C1MSK

I2C2RCV

I2C2TRN

I2C2BRG

I2C2CON

0208

020A

020C

0210

0212

0214

0216

ACKSTAT TRSTAT

—

BCL

—

GCSTAT ADD10

IWCOL

0000

00FF

0000

1000

—

Address Register

—

Address Mask Register

—

Receive Register

Transmit Register

—

Baud Rate Generator Register

I2CEN

I2CSIDL SCLREL IPMIEN

A10M

DISSLW

SMEN

GCEN

STREN

I2COV

ACKDT ACKEN

D/A

RCEN

PEN

R/W

RSEN

RBF

SEN

TBF

I2C2STAT

I2C2ADD

I2C2MSK

0218

021A

021C

ACKSTAT TRSTAT

—

BCL

—

GCSTAT ADD10

IWCOL

0000

—

Address Register

—

Address Mask Register

Legend:

— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 4-10: UART REGISTER MAPS

All

Resets

File Name Addr

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

U1MODE

U1STA

0220

UARTEN

—

USIDL

IREN

—

RTSMD

—

UEN1

UEN0

WAKE

LPBACK

ABAUD

RXINV

RIDLE

BRGH

PERR

PDSEL1 PDSEL0 STSEL

FERR OERR URXDA

0000

0110

xxxx

0000

0110

xxxx

0000

0222 UTXISEL1 UTXINV UTXISEL0

UTXBRK UTXEN

UTXBF

TRMT URXISEL1 URXISEL0 ADDEN

U1TXREG

U1RXREG

U1BRG

0224

0226

0228

0230

—

Transmit Register

Receive Register

—

Baud Rate Generator Prescaler Register

U2MODE

U2STA

UARTEN

—

USIDL

IREN

—

RTSMD

—

UEN1

UEN0

WAKE

LPBACK

ABAUD

RXINV

RIDLE

BRGH

PERR

PDSEL1 PDSEL0 STSEL

FERR OERR URXDA

0232 UTXISEL1 UTXINV UTXISEL0

UTXBRK UTXEN

UTXBF

TRMT URXISEL1 URXISEL0 ADDEN

U2TXREG

U2RXREG

U2BRG

0234

0236

0238

—

Transmit Register

Receive Register

—

Baud Rate Generator Prescaler Register

Legend:

— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

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