PIC24FJ64GA104 FAMILY
FIGURE 18-5:
MASTER MODE, PARTIALLY MULTIPLEXED ADDRESSING (SEPARATE READ
AND WRITE STROBES, SINGLE CHIP SELECT)
PIC24F
PMA<10:8>
PMD<7:0>
PMA<7:0>
PMCS1
PMALL
PMRD
PMWR
Address Bus
Multiplexed
Data and
Address Bus
Control Lines
FIGURE 18-6:
MASTER MODE, FULLY MULTIPLEXED ADDRESSING (SEPARATE READ AND
WRITE STROBES, SINGLE CHIP SELECT)
PMD<7:0>
PMA<7:0>
PMA<15:8>
PIC24F
PMCS1
PMALL
PMALH
PMRD
PMWR
Multiplexed
Data and
Address Bus
Control Lines
FIGURE 18-7:
EXAMPLE OF A MULTIPLEXED ADDRESSING APPLICATION
PIC24F
PMD<7:0>
PMALL
A<7:0>
373
A<15:0>
D<7:0>
D<7:0>
CE
A<15:8>
373
OE
WR
PMALH
PMCS1
PMRD
PMWR
Address Bus
Data Bus
Control Lines
FIGURE 18-8:
EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION
PIC24F
A<7:0>
373
PMD<7:0>
PMALL
A<10:0>
D<7:0>
D<7:0>
CE
A<10:8>
PMA<10:8>
OE
WR
Address Bus
Data Bus
PMCS1
PMRD
PMWR
Control Lines
2010 Microchip Technology Inc.
DS39951C-page 199