PIC24FJ64GA104 FAMILY
FIGURE 18-2:
LEGACY PARALLEL SLAVE PORT EXAMPLE
Address Bus
Data Bus
PIC24F Slave
Master
PMD<7:0>
PMD<7:0>
Control Lines
PMCS1
PMRD
PMWR
PMCS1
PMRD
PMWR
FIGURE 18-3:
ADDRESSABLE PARALLEL SLAVE PORT EXAMPLE
PIC24F Slave
Master
PMA<1:0>
PMA<1:0>
Write
Address
Decode
Read
Address
Decode
PMD<7:0>
PMD<7:0>
PMDOUT1L (0)
PMDIN1L (0)
PMDIN1H (1)
PMDIN2L (2)
PMDIN2H (3)
PMCS1
PMRD
PMWR
PMCS1
PMRD
PMWR
PMDOUT1H (1)
PMDOUT2L (2)
PMDOUT2H (3)
Address Bus
Data Bus
Control Lines
TABLE 18-1: SLAVE MODE ADDRESS RESOLUTION
PMA<1:0>
Output Register (Buffer)
Input Register (Buffer)
00
01
10
11
PMDOUT1<7:0> (0)
PMDOUT1<15:8> (1)
PMDOUT2<7:0> (2)
PMDOUT2<15:8> (3)
PMDIN1<7:0> (0)
PMDIN1<15:8> (1)
PMDIN2<7:0> (2)
PMDIN2<15:8> (3)
FIGURE 18-4:
MASTER MODE, DEMULTIPLEXED ADDRESSING (SEPARATE READ AND
WRITE STROBES, SINGLE CHIP SELECT)
PIC24F
PMA<10:0>
PMD<7:0>
PMCS1
PMRD
PMWR
Address Bus
Data Bus
Control Lines
DS39951C-page 198
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
