PIC24FJ64GA104 FAMILY
REGISTER 9-2:
DSWAKE: DEEP SLEEP WAKE-UP SOURCE REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0, HS
DSINT0(1)
bit 15
bit 8
R/W-0, HS
DSFLT(1)
bit 7
U-0
—
U-0
—
R/W-0, HS
DSWDT(1)
R/W-0, HS
DSRTC(1)
R/W-0, HS
DSMCLR(1)
U-0
—
R/W-0, HS
DSPOR(2)
bit 0
Legend:
HS = Hardware Settable bit
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 15-9
bit 8
Unimplemented: Read as ‘0’
DSINT0: Interrupt-on-Change bit(1)
1= External Interrupt 0 was asserted during Deep Sleep
0= External Interrupt 0 was not asserted during Deep Sleep
bit 7
DSFLT: Deep Sleep Fault Detected bit(1)
1= A Fault occurred during Deep Sleep and some Deep Sleep configuration settings may have been
corrupted
0= No Fault was detected during Deep Sleep
bit 6-5
bit 4
Unimplemented: Read as ‘0’
DSWDT: Deep Sleep Watchdog Timer Time-out bit(1)
1= The Deep Sleep Watchdog Timer timed out during Deep Sleep
0= The Deep Sleep Watchdog Timer did not time out during Deep Sleep
bit 3
bit 2
DSRTC: Real-Time Clock and Calendar Alarm bit(1)
1= The Real-Time Clock and Calendar triggered an alarm during Deep Sleep
0= The Real-Time Clock and Calendar did not trigger an alarm during Deep Sleep
DSMCLR: Deep Sleep MCLR Event bit(1)
1= The MCLR pin was asserted during Deep Sleep
0= The MCLR pin was not asserted during Deep Sleep
bit 1
bit 0
Unimplemented: Read as ‘0’
DSPOR: Power-on Reset Event bit(2)
1= The VDD supply POR circuit was active and a POR event was detected
0= The VDD supply POR circuit was not active, or was active, but did not detect a POR event
Note 1: This bit can only be set while the device is in Deep Sleep mode.
2: This bit can be set outside of Deep Sleep.
DS39951C-page 118
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
